It would be useful to have an option in Icarus Verilog to generate VCD variable names without shortening them. Basically I'd like to have VCD file "prolog" to declare acronyms to be the same as actual variable names, and have Iverilog generate sections of VCD file with long names. This would (1) create extremely big names and big VCD files (2) let me to save myself lots of time for writing boring $write("new_variable=%x", new_variable) for each newly added variable which I want to monitor.
Basically I'd like to use feature of VCD for spitting only variables that change in a given cycle to serve me. I'd like to have VCD file to be human readable, so that I can see which signals change where in a given cycle without using a waveform viewer.