#46 Add meaningful names for VCD variables

open
nobody
2
2012-06-13
2012-06-13
No

It would be useful to have an option in Icarus Verilog to generate VCD variable names without shortening them. Basically I'd like to have VCD file "prolog" to declare acronyms to be the same as actual variable names, and have Iverilog generate sections of VCD file with long names. This would (1) create extremely big names and big VCD files (2) let me to save myself lots of time for writing boring $write("new_variable=%x", new_variable) for each newly added variable which I want to monitor.

Basically I'd like to use feature of VCD for spitting only variables that change in a given cycle to serve me. I'd like to have VCD file to be human readable, so that I can see which signals change where in a given cycle without using a waveform viewer.

Discussion

    • priority: 5 --> 2
     
  • It's not hard to implement this behaviour. The attached patch is a starting point - it just needs extending to make the behaviour switchable at run time, not compile time.

     
  • Patch to generate human-readable signal IDs in VCD files

     
    Attachments
  • Martin,

    I gave your patch a try.

    This is exactly what I wanted.

    Now that I think about it, I just see two approaches (a) work on your patch for VCD (b) implement another sys_* file for output other than VCD, which would be easily grep'able...

    Could we turn your patch into valid Icarus Verilog option (command line switch) instead of static define?

    Wojciech