#44 support for SystemVerilog "interface"

open
5
2014-12-19
2012-04-15
Iztok Jeras
No

Hi,

The interface in the example implements a simple handshake protocol (request/grant). The interface connects a request source to a drain which grants the requests. LFSR are used to randomize the request and grant signal. All three (source, interface, drain) count the number of granted requests. The test checks if this three numbers are in agreement before it finishes. Modports are used to prevent the source/drain instances from accessing the interface internal counter.

Use the example code from: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_interface.v && vvp a.out
or the attached file.

Regards,
Iztok Jeras

Discussion

  • Iztok Jeras
    Iztok Jeras
    2012-04-15

    example Verilog code

     
    Attachments
  • Cary R.
    Cary R.
    2013-09-13

    I have been looking at interfaces a bit to get an understanding of how they should work. One question I have so far is for the case that the module declaration only specifies the interface and the instantiation of the module specifies which modport to use, can different instantiations of the same module use a different modport?

    Basically look at the example in section 25.5 on page 718 in IEEE Std 1800-2012 and imagine calling a second instantiation of one of the modules with a different modport. If the modports are required to match this is easier to implement, but the standard does not specifically require this and it makes some sense that you may want to use different modports that have the same basic API in the same module. Doing this requires that any modports used in the instantiation be compatible with the module definition, but they may not need to be identical. This gains further flexibility when interface tasks/functions from section 25.7 are considered.

    I can help create an example if needed.

     
  • Iztok Jeras
    Iztok Jeras
    2013-09-15

    Hi Cary,

    There are many complaints regarding the modport specification. The Synplify tool went as far as to ignore modport IO directions in synthesis (this might have been fixed now, I would have to check the latest documentation). Making things harder is the option to mix port definitions with and without modports.

    One good source of modport examples might be the UVM specification, it uses interfaces extensively in both bench and RTL modules (just search for the interface keyword int the examples).
    http://www.accellera.org/downloads/standards/uvm/uvm-1.1d.tar.gz

    Regards,
    Iztok Jeras

     
    • assigned_to: Martin Whitaker
     
  • I'm working on this now. As a first step, I've just pushed changes to allow interfaces to be declared and instantiated. modport declarations are not yet supported.