The SystemVerilog feature "Parameter type" is not yet supported, I created a test for it. The provided test creates various instances of a module where one of the ports has a parameterized type. This parameter is different for each module instance. Modules report back the width of the parameterized port, this width is then used to check if the tested feature works as expected.
Use the example code from: https://github.com/jeras/ivtest/tree/test_sv
iverilog -g2009 ivltests/sv_parameter_type.v && vvp a.out
or the attached file.