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Please browse the reported bugs/issues for Icarus Verilog at your pleasure. If you think you have found a bug of your own, first browse the existing bugs and feature requests to determine whether your bug has already been reported by someone else. It is far better to expound on an existing bug report then to create a new bug report for the same thing. If you find that your issue matches an existing report, then click on that issue page to get details. You have the option of adding comments to the bug report. Also, you will be able to monitor any existing bug report. If you have convinced yourself that your bug really is unique, then use the Submit link to start the bug submission.

The priority breakdown reflects the priority that the Icarus Verilog development team intends given the nature of the problem. This is how the Icarus Verilog team assigns priority:

3 - minor issues like invalid or missing warnings, spelling fixes, etc.

4 - functionality that is missing, but is not currently needed or can be worked around with code changes,

5 - The catch all for run-of-the-mill bugs, or unreviewed bugs,

6 - an invalid result without a warning that can be worked around; or use this priority for a program crash that is preventing one from using Icarus Verilog,

7 - An invalid result without a warning that cannot be worked around reasonably.

9 - Imminent nuclear death, meteor impact, or hysterical screaming boss.

The "Owner" field is used by the core Icarus Verilog developers to claim a bug report. Somebody may be working on unassigned reports, but when it is assigned then that individual is explicitly stating that they are (intend) to work on it. If you wish to contribute towards fixing a claimed bug report, please coordinate with the claimant.

v0.8

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88 iverilog fails to compile simplyrisc-s1 sources v0.8 closed-fixed 2006-10-20 2006-12-01 5  
80 addition expression width problem v0.8 closed-out-of-date 2006-10-04 2009-03-23 4  
77 syntax error in produced vvp file v0.8 closed 2006-09-28 2006-10-04 5  
74 $display(y[1<<2]) != $display(y[4]) v0.8 closed-fixed 2006-09-19 2006-09-20 5  
72 No compilation, odd output v0.8 closed-works-for-me 2006-08-30 2006-09-23 5  
65 easily fixed typo in vvp/schedule.cc v0.8 closed-fixed 2006-08-06 2006-08-06 5  
60 problem with $setuphold on bus signal v0.8 closed-fixed 2006-07-11 2006-12-03 5  
58 valid program(?) causes internal error & other errors v0.8 closed-wont-fix 2006-07-01 2014-12-22 4  
54 verilog.spec v0.8 closed-fixed 2006-06-19 2006-06-24 5  
53 Synthesis fails for user defined functions v0.8 open 2006-06-15 2009-01-27 4  
47 assertion at run-time when performing wide / or % v0.8 closed-out-of-date 2006-05-16 2009-03-23 4  
46 assertion from compiler when using unary negation v0.8 closed-fixed 2006-05-16 2007-07-19 4  
36 ./configure files missing in v0_8-branch v0.8 closed-works-for-me Stephen Williams 2006-04-20 2006-04-20 5  
35 buggy compilation: "UNSUPPORTED LOGIC TYPE: 20" v0.8 closed Stephen Williams 2006-04-20 2006-12-31 7  
34 error: ...if statement is missing the else clause... v0.8 closed-fixed Stephen Williams 2006-04-11 2006-04-16 7  
20 Inaccurate handling of the `include directive v0.8 closed Stephen Williams 2006-01-23 2006-02-07 5  
9 dup_expr() const: Assertion `0' failed v0.8 closed-out-of-date 2005-10-31 2005-11-26 5  
8 dup_expr() const: Assertion `0' failed v0.8 closed-out-of-date 2005-10-31 2005-11-26 5  
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