Please browse the reported bugs/issues for Icarus Verilog at your pleasure. If you think you have found a bug of your own, first browse the existing bugs and feature requests to determine whether your bug has already been reported by someone else. It is far better to expound on an existing bug report then to create a new bug report for the same thing. If you find that your issue matches an existing report, then click on that issue page to get details. You have the option of adding comments to the bug report. Also, you will be able to monitor any existing bug report. If you have convinced yourself that your bug really is unique, then use the Submit link to start the bug submission.
The priority breakdown reflects the priority that the Icarus Verilog development team intends given the nature of the problem. This is how the Icarus Verilog team assigns priority:
3 - minor issues like invalid or missing warnings, spelling fixes, etc.
4 - functionality that is missing, but is not currently needed or can be worked around with code changes,
5 - The catch all for run-of-the-mill bugs, or unreviewed bugs,
6 - an invalid result without a warning that can be worked around; or use this priority for a program crash that is preventing one from using Icarus Verilog,
7 - An invalid result without a warning that cannot be worked around reasonably.
9 - Imminent nuclear death, meteor impact, or hysterical screaming boss.
The "Owner" field is used by the core Icarus Verilog developers to claim a bug report. Somebody may be working on unassigned reports, but when it is assigned then that individual is explicitly stating that they are (intend) to work on it. If you wish to contribute towards fixing a claimed bug report, please coordinate with the claimant.
|67||Snapshot 20060809 won't build on cygwin||devel||closed-fixed||2006-08-16||2006-09-20||5|
|66||RPM installs man page in /usr/man, should be /usr/share/man||devel||closed-fixed||2006-08-10||2006-10-04||5|
|64||parameter assignment does not support power function (**)||devel||closed-fixed||2006-07-28||2006-07-31||5|
|63||Modulus of reals should generate an error||devel||closed-fixed||2006-07-25||2006-08-09||5|
|62||signed variable bit shift gives incorrect answer||devel||closed-fixed||2006-07-14||2006-07-30||5|
|57||Constants are incorrectly extended||devel||closed-fixed||2006-06-30||2006-07-07||5|
|56||can't mix parameters and array of instances||devel||closed-fixed||2006-06-22||2008-08-01||5|
|55||vvp: internal error: port 0 expects wid=4, got wid=5||devel||closed-fixed||2006-06-19||2006-11-26||5|
|52||signed math in assign/wire does not behave as signed||devel||closed-fixed||2006-05-25||2006-06-20||5|
|51||unusual delay handling||devel||closed-fixed||2006-05-20||2006-06-02||5|
|50||$realtobits system function||devel||closed-fixed||2006-05-19||2006-06-18||5|
|49||CVS 05/12/06 coredumps in PEConcat||devel||closed-fixed||2006-05-17||2006-05-19||5|
|48||assertion: a.size() == b.size()||devel||closed-fixed||2006-05-17||2006-05-24||5|
|44||Part select of non-zero based vectors is wrong||devel||closed-fixed||2006-04-29||2006-05-01||7|
|43||Concatenations as args to inout ports||devel||closed-fixed||2006-04-28||2006-04-28||5|
|42||Release after force of variable causes assertion||devel||closed-fixed||2006-04-26||2006-08-04||6|
|41||C99 lround not always available||devel||closed-fixed||2006-04-26||2006-04-28||5|
|39||assign bit vector overflow run time error||devel||closed-fixed||2006-04-21||2006-04-26||5|
|37||v2k : task does not support ansi io||devel||closed-fixed||2006-04-21||2006-05-11||5|
|33||problem with generate for||devel||closed-fixed||2006-04-10||2006-04-12||5|
|32||parse error in specify block||devel||closed-fixed||2006-04-10||2006-04-17||5|
|31||simulation error, sig goes X||devel||closed-fixed||2006-04-10||2006-05-18||5|
|30||v2001 bit select syntax wont compile on lhs of =||devel||closed-fixed||2006-04-06||2006-04-16||5|
|28||verilog-20060215 does not compile with gcc version 4.1.0 pre||devel||closed-fixed||2006-03-25||2006-03-25||5|