#932 string type as an input into a task

devel
closed-fixed
nobody
None
5
2013-06-20
2013-06-02
Iztok Jeras
No

Hi,

Transferring a string to a task, as an input of type 'string' does not work, an empty string is seen instead. For debugging purposes I also tried to use the $typename system function, which is not implemented yet, it is commented out it the example. The Example works properly in ModelSim.

compile using Icarus Verilog

iverilog -g2012 string_bug.sv
vvp a.out

compile using ModelSim

vlib work
vlog string_bug.sv
vsim -c -do 'run -all; quit' string_bug

The purpose of the original code was to open a named pipe ($ mkfifo pipename.fifo) for an UART model. Here ModelSim also failed, it locked into a loop while opening the pipe file.

Regards,
Iztok Jeras

1 Attachments

Discussion

  • I've pushed a fix for the initial problem. However this has exposed a second bug - $fopen doesn't accept a 'string' argument.

     
    • Cary R.
      Cary R.
      2013-06-14

      Martin,

      Are you going to also fix the $fopen() bug? I'm guessing there could be a number of other system tasks/functions that should take a string that currently fail since the string type is a fairly new addition to Icarus.

       
  • Yes, I'll push a fix shortly. The fix is fairly generic, so should cover other system tasks/functions.

     
  • Fix pushed to git master.

     
    • status: open --> closed-fixed
     
  • Iztok Jeras
    Iztok Jeras
    2013-06-20

    Hi Martin,

    There is another related issue, 'string' is not accepted as the type of a parameter. Since it seems 'int' is accepted this could be at least a parser (lexer) issue.

    For example the next code:

    module tb #(
    parameter string FILENAME_TX = "uart_txd.fifo"
    );
    ...
    endmodule

    Would report an error:

    ../tbn/tb_Terasic_DE1.sv:4: syntax error
    I give up.

    Regards,
    Iztok Jeras

     
    • Hi Iztok,

      This one's a bit different. Apart from the 2-state integer types, there is currently no support for the new SystemVerilog types in parameter declarations. I don't know where this sits on Steve's priority list - we can ask. I suspect it would be fairly straightforward to at least support enumerations and strings, so if Steve isn't planning to work on it in the near future, I could take a look at it.