#931 loop is repeated without waiting for clock posedge

devel
closed-fixed
None
7
2013-09-16
2013-05-25
Iztok Jeras
No

This is probably a scheduler issue, maybe related to the fork/join statement.

To repeat, please do:
$ git clone https://github.com/jeras/butterflylogic.git
$ git checkout 5390c5b00ea4e93bb0821231adb4f10f98f3336f
$ cd butterflylogic/sim
$ make -f Makefile.iverilog WAVE=1 rle

For a correct simulation I used Modelsim Altera edition:
$ make -f Makefile.modelsim WAVE=1 rle

To see the difference, observe where the tb_rle.error counter is incremented. The issue is the loop at line 81 in tbn/tb_rle.sv should count only after clock posedge, instead 'sto_cnt' goes from 3 to 4 without a clock posedge.

I do not have the time to create a more compact example now. I will use ModelSim for some time then get back to this bug.

Regards,
Iztok Jeras

Discussion

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  • I've taken a quick look at this, and it does appear to be a problem with fork/join. Attached is a simple test case that exposes the bug. The fault occurs when the first thread of the fork terminates whilst the second thread is inside a task. The bug is only in development; V0.9 executes this test case correctly.

     
    Attachments
    • assigned_to: Martin Whitaker
     
  • I've pushed a fix for this to github.

     
    • status: open --> closed-fixed
     
    • status: closed-fixed --> open
     
  • Belay that - looks like I've only fixed part of the problem!

     
    • status: open --> closed-fixed
     
  • Should be fully fixed now.

     
  • Iztok Jeras
    Iztok Jeras
    2013-09-15

    I still have issues with similar code, maybe the issue was fixed but there is a regression. This time I created shorter example files. Basically there is a stream source and a stream drain with valid/ready handshaking signals. Inside a fork 4 source and 4 drain cycles are requested. Waveforms should be observed to see the issue.

    There are 2 issues visible:
    1. at the end of the last transfer the 'drn' module should put 'tready' into an inactive state
    2. received data should properly show inside the 'dat' signal

    To run the example in Icarus do:

    iverilog -g2012 iverilog_test.sv str.sv
    vvp a.out
    gtkwave waves.dump
    

    To run the example using ModelSim do:

    vlib work
    vlog iverilog_test.sv str.sv
    vsim -c -do 'run -all; quit' iverilog_test
    gtkwave waves.dump
    

    Regards,
    Iztok Jeras

     
    Attachments
    • Cary R.
      Cary R.
      2013-09-16

      This latest code has a race condition related to tvalid. After adding a simple watchdog and using the -pfileline=1 flag to observe how the procedural code is executed. The following is how this is executing with Icarus:

      tvalid = 1'b0 in str_src.trn
      while (~tvalid) @ (posedge clk) in str_drn.trn
      tvalid = 1'b1 in str_src.trn

      Adding some delay (e.g. @ (negedge clk) ) before the tvalid = 1'b0 assignment avoids the race by causing the statement in str_drn.trn to run before tvalid is set to zero, but this change may not work as you intended.

       
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