This is probably a scheduler issue, maybe related to the fork/join statement.
To repeat, please do:
$ git clone https://github.com/jeras/butterflylogic.git
$ git checkout 5390c5b00ea4e93bb0821231adb4f10f98f3336f
$ cd butterflylogic/sim
$ make -f Makefile.iverilog WAVE=1 rle
For a correct simulation I used Modelsim Altera edition:
$ make -f Makefile.modelsim WAVE=1 rle
To see the difference, observe where the tb_rle.error counter is incremented. The issue is the loop at line 81 in tbn/tb_rle.sv should count only after clock posedge, instead 'sto_cnt' goes from 3 to 4 without a clock posedge.
I do not have the time to create a more compact example now. I will use ModelSim for some time then get back to this bug.