Was running a testbench today and noticed that this statement:
if (dec_5_0.yout_ph1 != 14'd6) begin $display("Mismatch ph1"); end
didn't print "Mismatch ph1" when yout_ph1 was X's. Changed it to ! around an == and same thing.
Is this correct Verilog semantics? I was under the impressions that both == and != should fail when present with X's, not succeed.