#923 tvhdl fail on DDR model

devel
closed-fixed
nobody
5
2013-04-12
2013-03-21
dtsao
No

I am trying to convert a verilog DDR model I downloaded from Micron to VHDL, using -tvhdl in Icarus, but it fails with the following error:

Assertion failed: (false), function create_skeleton_entity_for, file scope.cc, line 954.
sh: line 1: 41869 Done /usr/local/lib/ivl/ivlpp -L -F"/var/folders/j5/cmlvj17x7tq31zkb07f32d100000gr/T//ivrlg229f0faad" -f"/var/folders/j5/cmlvj17x7tq31zkb07f32d100000gr/T//ivrlg29f0faad" -p"/var/folders/j5/cmlvj17x7tq31zkb07f32d100000gr/T//ivrli29f0faad"
41870 Abort trap: 6 | /usr/local/lib/ivl/ivl -C"/var/folders/j5/cmlvj17x7tq31zkb07f32d100000gr/T//ivrlh29f0faad" -C"/usr/local/lib/ivl/vhdl.conf" -- -

Does anyone know what this means?

Discussion

  • It means the VHDL code generator has encountered an unexpected Verilog construct. Looking at the source code where the assertion was triggered, it is likely to be in a parameter declaration. Looking at the VHDL code generator limitations documented at

    http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator

    (and knowing something about the Micron DDR models), my guess is that it is a real-valued parameter that is causing the problem. I can trigger the same assertion with the following simple test case:

    module vhdlTest();

    localparam RealValue = 2.0;

    endmodule

    I've never looked at the VHDL code generator, so don't know how much work would be required to add support for real variables. I would guess it is not trivial, otherwise it would have been done already. We should at least output a proper error message saying this is an unsupported construct, rather than triggering an assertion.

     
  • Cary R.
    Cary R.
    2013-03-22

    Adding real support may not be as hard as you think. Nick focused on bit vectors and never got around to adding any code for real variables, etc. It may not be easy, but I would not make the assumption that just because it is not there that it would be hard to add. The problem with the VHDL code generator is it is basically orphaned.

     
    • status: open --> closed-fixed
     
  • I've pushed a fix for this to git master. I've also fixed another VHDL code generator crash exposed by the Micron ddr3 Verilog model. Note that Icarus still cannot successfully translate the Micron model (for a number of reasons), but at least it now tells you why.