Attached test shows a miscompile in the test. To confirm the error I checked the output on other simulators. ModelSim and GPL Cver confirm that iverilog has a miscompile. I tried other versions of iverilog and in all cases (include git trunk) I saw the same error.
test.v is a test for miscompile.
To compile it I simply used command 'iverilog test.v'. I believe that the execution of assignment ''mem_p_addr0 <= in_data; //bug" is not correct. Picture wave.jpg shows that error.
File data.txt contains input data. File expected-result.txt contains correct output for the test.
File test-description.c describes the behavior of the state-machine in test_module. It will be helpful if you would like to understand the control flow of the state-machine in order to fix bug.