Work at SourceForge, help us to make it a better place! We have an immediate need for a Support Technician in our San Francisco or Denver office.

Close

#876 Probably wrongly generated vcd file

v0.9
closed-invalid
nobody
Other (110)
5
2012-01-07
2011-12-27
avi9526
No

OS: Ubuntu 11.10 desktop amd64
iverilog: 0.9.4 (from Ubuntu repository), 0.9.5 (compiled from source)
Used iverilog to simulate my code. This code not finished and have many errors and probably totally invalid. But vcd waveform-file that was generate with Modelsim is different from file generated with iverilog.

Discussion

  • avi9526
    avi9526
    2011-12-27

    archive with verilog code, run simulation shell-script, result of simulation, and picture to illustrate problem

     
    Attachments
  • Cary R.
    Cary R.
    2012-01-03

    I don't have time to dig in and debug this right now, but this kind of problem is almost always caused because of a timing race (e.g. changing and sampling a signal on the same edge). If this is the case then different simulators are allowed to produce different results since the order expressions are evaluated is undefined. A non-blocking assignment <= usually fixes this for signals inside the RTL, but the test interface can have have problems if you are not careful. You can also have problems with derived clocks since they and the data may both change in the same delta cycle.

    Please look for something like the above that is related to the signals that are having problems. It is also best to change a signal on the inactive edge or with an appropriate setup/hold time which avoids this problem and also makes the test suite compatible with gate level simulations.. If you can't figure this out we'll try to look at this when we have some free time. Please let us know if you do figure it out so we can close the bug report.

     
  • avi9526
    avi9526
    2012-01-03

    I checked that what you said and found the problem, I inadvertently used a blocking assignment where must be used non-blocking assignement, this led to the unexpected (for me) result. Also the similar problem was in test module. IVerilog has a problem with blocking assignments or is it acceptable?
    Solved for me, thanks for support!

     
  • Cary R.
    Cary R.
    2012-01-03

    Without knowing the exact details I can't say for sure, but it is very likely Icarus is working correctly and the difference between the two simulators is acceptable because the order of evaluation is not and cannot be defined.

    Think of it this way, if you have two always block which one is evaluated first? The answer is you don't know and if your code produces different results depending on the evaluation order then different simulators may give different results. For the real circuit they will likely evaluate in parallel and have some intrinsic delay, but that's not how Verilog works.

    I'll leave this open for a while so you can respond, but I'll close it in a week or so.

     
  • Cary R.
    Cary R.
    2012-01-03

    • status: open --> open-invalid
     
  • Judging by the comments, I'd say this report is closed. Re-open it if you believe otherwise.

     
    • status: open-invalid --> closed-invalid