If I declare an array,e.g.:
reg [7:0] data [7:0]
and then if out [7:0] is an output of the module where the array is declared,
assign out = data,
then data becomes an array and I have only the LSB of the "register" data
You don't say which version of 0.8 you are using. V0.8 is an older unsupported version. The current stable release is V0.9.2. I tested an example like this using the latest V0.8 (0.8.7) and it worked there along with all the recent versions (V0.9 and development).
I am going to close this as an invalid report. If you believe I have missed something then please provide a complete example that demonstrates the problem. Code snippets are helpful in the details section, but we really like to have a complete example attached to the report. Occasionally the issue is not what the original poster thought it was.
My guess is that somewhere in the path you have the width incorrect and that is truncating the result. It is best to use $monitor or use a waveform viewer to see exactly what is going on at the various levels of your circuit.