#613 High precision in timescale does not simulate correctly

v0.9
closed-fixed
5
2009-01-06
2009-01-04
Trevor Williams
No

Given the following example, the second assignment to 'a' never occurs. I have also witnessed the same issue when the timescale is as precise as "1 s / 1 ns".

`timescale 1 s / 1 fs

module main;

reg a;

initial begin
a = 1'b0;
#10;
a = 1'b1;
end

initial begin
`ifdef DUMP
$dumpfile( "timescale1.18.vcd" );
$dumpvars( 0, main );
`endif
#100;
$finish;
end

endmodule

Discussion

  • Cary R.
    Cary R.
    2009-01-05

    I am getting the second assignment, but there are some weird things going on. It looks like the assignment is happening at the wrong time and there is a known issue with the $monitor I'm using and large delays (I'm working on this). The problem appears to be in the compiler since the a.out file has the wrong delay value, but I'm guessing other problem will appear as we look at this in more detail. I'm not setting this to V0.9 until we know the scope of the problem. If it is not too hard we may be able to fix this before the release, otherwise it will go into the next development (V0.10). Based on some simple testing this looks like a 32/64 bit issue. This may only fail on a 32 bit machine.

     
  • This looks like an overflow of the time value as passed to the %delay instruction. When the time is specified in scope units, the compiler converts it to simulation precision, which is this case is 1fs. The value 10s is 10,000,000,000,000. That is 10 terra-ticks. Not all of the path from source code through to the run time is 64bit clean for time values.

     
    • assigned_to: nobody --> stevewilliams
     
    • milestone: 530321 --> v0.9
     
    • status: open --> closed-fixed
     
  • Fixed in git master.