Hi,
Details of the bug follows:
<code>
module bug04_integerDiv;
reg signed[31:0] reg0;
reg signed[31:0] reg1;
wire signed[31:0] dividend=reg0;
wire signed[31:0] divisor=reg1;
wire signed[31:0] quotient;
assign quotient= dividend/divisor;
initial begin
reg0=32'h76c3625e;
reg1=32'hffffffff;
//BUG here: quotient==32'hxxxxxxxx, should be 32'h893c9da2
#100 $display("dividend=%h divisor=%h quotient=%h expected output=893c9da2",dividend,divisor,quotient);
$display("reg0=%h reg1=%h reg0/reg1=%h expected output=893c9da2",reg0,reg1,reg0/reg1);
end
endmodule
</code>
I know that normally in synthesis the divisor can be only powers of 2. But it should work for other numbers than powers of 2 according to the verilog language specification (if it isn't synthesis).
I am using version 0.8.6.
Best Regards,
Sadi.
Şadi Çağatay Öztürk
2008-11-07
Cary R.
2008-11-07
This is also failing in devel so I'm switching this to devel and we will switch it back once devel is fixed. Hopefully the patch is similar. There are two problems in devel. One is that it is not catching divide by zero and is giving a floating point exception (V0.8 appears to be doing this, but I need to double check). I already have a fix for this. The other problem is that the conversion of -1 into a 1 is incorrectly producing 0. This appears to be a problem with shifting a 32 bit value by 32 bit. The remainder error is likely the same problem since it uses the same code.
Cary R.
2008-11-07
Cary R.
2008-11-08
Cary R.
2008-11-08
I have submitted a patch for the development branch that fixes this problem and more. I'm returning the report to V0.8.
Cary R.
2008-11-14
Cary R.
2008-11-14
I submitted a patch based on the one from development that fixes this for V0.8. Wide support is still not available, but that is covered by a different report.