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#242 Part select of signal ports not implemented

v0.9
closed-fixed
4
2008-12-12
2007-05-22
Evan Lavelle
No

The attached program tests a number of requirements for 95-style module ports. The expected output is listed at the top of the program.

The code runs correctly on ModelSim and ISE. cver reports 12 errors and 17 warnings, while both Icarus and Veriwell core dump.

Discussion

  • Evan Lavelle
    Evan Lavelle
    2007-05-22

    Verilog source code

     
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    one big vendors verilog simulator reports

    ERROR "expression given for a null module port"

    for m2/m3/m6/m18/m22 ....

     
  • Cary R.
    Cary R.
    2007-08-16

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    Running this with the latest devel does not crash and 19 of the 23 locations have the correct result! It does give some warnings about unconnected port bits which should be fine. The real problem is likely the other warning messages "Forgot to implement part select of signal port."

     
  • Cary R.
    Cary R.
    2007-08-20

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    The test file does not declare the vector width on the input/output declarations so the fix from pr1704013 will now cause this code to have fatal errors. Once pr1704013 is cleaned up you can use the appropriate flag to get the file to run as is or the declarations can be fixed if you want to run the file before then.

     
  • Cary R.
    Cary R.
    2007-08-22

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    Using the new patchs to pr1704013 and the new -gno-io-range-error flag this now runs as I previously mentioned.

     
  • Cary R.
    Cary R.
    2008-02-21

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    Changed the summary line and priority to reflect the new guidelines.

     
  • Cary R.
    Cary R.
    2008-02-21

    • priority: 5 --> 4
    • summary: Problems with complex 95-style module ports --> Part select of signal ports not implemented
     
  • Cary R.
    Cary R.
    2008-12-12

    • milestone: 530321 --> v0.9
     
    • assigned_to: nobody --> stevewilliams
     
    • status: open --> closed-fixed
     
  • Fixed in git master.