Re: [Gumstix-users] gumstik hardware suggestions

[Zach W. <zw...@su...>]

Phil Wilshire wrote:
> I would like to use the stik as a teaching tool but I need JTAG for 
> this.

I wish I could be in that class, that is *my* kind of learnin'! :)

> Pads for LEDs and switches on the dboard would also be very useful 
> for projects and students.

Certainly, a more generally reconfigurable daughterboard would be easy
to make for a lab setting.  My suggestions were specifically aimed at
the Waysmall device.  However, this reminded me of the JTAG board Gordon
is making for us... certainly, I would like us to consider these *exact*
options for such a design.  I'd add an 8-segment LED display and 3:8
decoder to the list to use for debugging.

> If we can expose the JTAG on the edge of the board, could we also 
> expose some other subsystems in the same manner.

To be clear, I do not intend these pads to be anything like a "connector
edge" -- simply the very bare minimum necessary to place a part.  I
suppose other 'solder points' could be exposed, but....  Looking at the
board, I sit and wonder how he did it in the first place, so I'm very
sympathetic to these demands.  It would be neat to see more exposed, but
this is really not the best way to do it.

I'd rather see the design switch to using a high density connector that
brought ought as much as electrically possible (except maybe the
processor bus itself).  However, there are 84 GPIO lines alone; that's
not going to have "quite" the same mechanical dimensions. Reality bites.

> Some extended gpio  would be really nice.

Just in case you (or others) missed this point, the pinout guide I
provided lists the 12 pins available on the header that can be used as
general purpose I/O bits.  Of course, this might detract somewhat from
their original function; however, the CTS/RTS pins give you four right
away that aren't "strictly" needed.  That effectively means there are
already 8 lines completely free (counting the NSSP port).

> My Jtag systems  do use 5 pins (in,out,clock,state,ground ) I also 
> have the reset pin wired up and I am sure it does something.

According to the specification published in the "Intel XScale
Microarchitecture User Manual" (Chapter 9, Section 2), one must assert
NRESET after or at the same time you assert NTRST (the TAP interface
reset signal).  Other systems notwithstanding, that's what the spec says
for PXA; both lines can be asserted with the same signal, but it shows
that we either need a 6-pin connector (TDI, TDO, TCK, TMD, NTRST, GND)
and NTRST needs to be internally tied to the standard processor RESET
line.  Does this sound correct?

Cheers,

Zach