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Re: [Gumstix-users] LCD (Something Wierd)
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From: Demetris Z. <fgc...@cy...> - 2006-06-07 06:12:28
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Yes Craig , something like that.
If i enable for the framebuffer to be 8 bit instead of 16 will this go =
away or i am wrong here?
----- Original Message -----=20
From: Craig Hughes=20
To: General mailing list for gumstix users.=20
Sent: Wednesday, June 07, 2006 3:20 AM
Subject: Re: [Gumstix-users] LCD (Something Wierd)
It was hard to see exactly what the lines look like, but they appeared =
to basically be vertical stripes which were off, approx every 8 pixel =
columns?
C
On Jun 6, 2006, at 4:40 PM, Demetris Zavorotnichenko wrote:
ok, it doesn't flicker anymore, i had it connected to a source where =
the power was drawn too much, but i still have these lines on the =
screen, why?
----- Original Message -----=20
From: Demetris Zavorotnichenko=20
To: Gumstix Sorce forge forum=20
Sent: Wednesday, June 07, 2006 1:55 AM
Subject: [Gumstix-users] LCD (Something Wierd)
OK, i have enabled the LCD but the image shows kinda strange and =
it flashes allot.
I am sending an attachment to understand what i mean.
Why is it doing this and how do i fix it?
Here is my LCCR
LCD Controller Control Register 0 (7-23)
LCCR0 0x00300879 00000000 00110000 00001000 =
01111001
LCCR0_ENB 1 LCD controller enable
LCCR0_CMS 0 LCD monochrome operation =
enable
LCCR0_SDS 0 LCD dual panel display enable
LCCR0_LDM 1 LCD disable done IRQ disable
LCCR0_SFM 1 LCD start of frame IRQ =
disable
LCCR0_IUM 1 LCD fifo underrun error IRQ =
disable
LCCR0_EFM 1 LCD end of frame IRQ disable
LCCR0_PAS 0 LCD active display enable
LCCR0_DPD 0 LCD send 8 pixel on L_DD[7:0] =
at each clock
LCCR0_DIS 0 LCD controller disable
LCCR0_QDM 1 LCD quick disable IRQ disable
LCCR0_PDD 0 LCD palette DMA request delay
LCCR0_BM 1 LCD branch start IRQ disable
LCCR0_OUM 1 LCD fifo underrun IRQ disable
LCD Controller Control Register 1 (7-26)
LCCR1 0x06040a7f 00000110 00000100 00001010 =
01111111
LCCR1_PPL 639 LCD pixels per line (+1)
LCCR1_HSW 2 LCD horizontal sync pulse =
width (+1)
LCCR1_ELW 4 LCD end of line pixel clock =
wait count (+1)
LCCR1_BLW 6 LCD beginning of line pixel =
clock wait coun
t (+1)
LCD Controller Control Register 2 (7-28)
LCCR2 0x000099df 00000000 00000000 10011001 =
11011111
LCCR2_LPP 479 LCD lines per panel (+1)
LCCR2_VSW 38 LCD vertical sync pulse width =
(+1)
LCCR2_EFW 0 LCD end of frame line clock =
wait count (+1)
LCCR2_BFW 0 LCD beginning of frame line =
clock wait coun
t (+1)
LCD Controller Control Register 3 (7-31)
LCCR3 0x04400003 00000100 01000000 00000000 =
00000011
LCCR3_PCD 3 LCD pixel clock divisor (+1)
LCCR3_ACB 0 LCD AC bias pin frequency =
(+1)
LCCR3_API 0 LCD AC bias pin transitions =
per interrupt
LCCR3_VSP 0 LCD L_FCLK vertical sync =
polarity active lo
w
LCCR3_HSP 0 LCD L_LCLK horizontal sync =
polarity active
low
LCCR3_PCP 1 LCD data sampled on falling =
edge of L_PCLK
LCCR3_OEP 0 LCD L_BIAS output enable =
active low
LCCR3_BPP 16 LCD bits per pixel
LCCR3_DPC 0 LCD double pixel clock rate =
at L_PCLK
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