> To answer my own question (how to flush the code cache)
> Syscall __ARM_NR_cacheflush (0x9F0002) seems to do it with R0 set to
> start, R1 set to end, and R2 set to 0 (CODE cache? 4 may mean data
> cache...R1 seems to be end, but could be the size of the region to
> I hacked this up mostly by trial and error... If anyone knows for real
> what the parameters are for cacheflush...Sorry, I am a linux idiot and
> can't find my own backside in the sources...
grep -r cacheflush arch/arm will help you find the source;
it is in arch/arm/kernel/traps.c where you can read this
* Flush a region from virtual address 'r0' to virtual address 'r1'
* _exclusive_. There is no alignment requirement on either address;
* user space does not need to know the hardware cache layout.
* r2 contains flags. It should ALWAYS be passed as ZERO until it
* is defined to be something else. For now we ignore it, but may
* the fires of hell burn in your belly if you break this rule. ;)
* (at a later date, we may want to allow this call to not flush
* various aspects of the cache. Passing '0' will guarantee that
* everything necessary gets flushed to maintain consistency in
* the specified region).
Hope this helps,
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