Thanks, that solved the problem.
Dave Hylands wrote:
>>I never quite understood how complex makefiles work so now I'm stuck on
>>a simple problem.
>>I want to build the driver module: foo.ko which depends on it's C file
>>foo.c and on functions declared in another C file lets say bar.c. I
>>can't get the makefile to link the two C files together. Basically, I
>>want to say:
>>foo.ko: foo.o bar.o
>Yeah - while this might work for "regular" stuff, the kernel wants
>things done in a fairly specific way. The correct way to indicate that
>your foo.ko file depends on multiple objects is to do something like
>obj-m = foo.o
>foo-objs := foo1.o bar.o
>What happens, is that linux will compile each of the individual object
>files and then links them together into a partialy linked object file.
>So, a consequence of this is that the base of your .ko file can't be
>the same name as any of the source files that go into it. So the foo
>in foo.o (that gets added to obj-m) needs to match the foo in
>foo-objs, and needs to not match the base of any of the objects files
>produced from c files.
>So you can't have foo.ko, foo.c and bar.c, but you could have foo.ko
>foo1.c, and bar.c, and that's what the example above assumes.
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