I have a LCD Samsung 4.3" (LTE430WQF0) + Verdex XM4-bt + ConsoleLCD-vx.
I change my bootargs variable to "console=ttyS0,115200n8 root=1f01 rootfstype=jffs2 reboot=cold,hard video=pxafb:mode:416x272-8,active" but my LCD don't show nothing.
How can I enable the LCD?

My Verdex release is:  1565
during the boot appears the msg:
pxa2xx-fb pxa2xx-fb: overriding resolution: 416x272
pxa2xx-fb pxa2xx-fb: overriding bit depth: 8
Console: switching to colour frame buffer device 69x24
My pxaregs LCC is:
LCD Controller Control Register 0 (7-23)
LCCR0                    0x00300cf8  00000000 00110000 00001100 11111000
LCCR0_ENB                         0  LCD controller enable
LCCR0_CMS                         0  LCD monochrome operation enable
LCCR0_SDS                         0  LCD dual panel display enable
LCCR0_LDM                         1  LCD disable done IRQ disable
LCCR0_SFM                         1  LCD start of frame IRQ disable
LCCR0_IUM                         1  LCD fifo underrun error IRQ disable
LCCR0_EFM                         1  LCD end of frame IRQ disable
LCCR0_PAS                         1  LCD active display enable
LCCR0_DPD                         0  LCD send 8 pixel on L_DD[7:0] at each clock
LCCR0_DIS                         1  LCD controller disable
LCCR0_QDM                         1  LCD quick disable IRQ disable
LCCR0_PDD                         0  LCD palette DMA request delay
LCCR0_BM                          1  LCD branch start IRQ disable
LCCR0_OUM                         1  LCD fifo underrun IRQ disable

LCD Controller Control Register 1 (7-26)
LCCR1                    0x0307a19f  00000011 00000111 10100001 10011111
LCCR1_PPL                       415  LCD pixels per line (+1)
LCCR1_HSW                        40  LCD horizontal sync pulse width (+1)
LCCR1_ELW                         7  LCD end of line pixel clock wait count (+1)
LCCR1_BLW                         3  LCD beginning of line pixel clock wait count (+1)

LCD Controller Control Register 2 (7-28)
LCCR2                    0x0204250f  00000010 00000100 00100101 00001111
LCCR2_LPP                       271  LCD lines per panel (+1)
LCCR2_VSW                         9  LCD vertical sync pulse width (+1)
LCCR2_EFW                         4  LCD end of frame line clock wait count (+1)
LCCR2_BFW                         2  LCD beginning of frame line clock wait count (+1)

LCD Controller Control Register 3 (7-31)
LCCR3                    0xc3700005  11000011 01110000 00000000 00000101
LCCR3_PCD                         5  LCD pixel clock divisor (+1)
LCCR3_ACB                         0  LCD AC bias pin frequency (+1)
LCCR3_API                         0  LCD AC bias pin transitions per interrupt
LCCR3_VSP                         1  LCD L_FCLK vertical sync polarity active low
LCCR3_HSP                         1  LCD L_LCLK horizontal sync polarity active low
LCCR3_PCP                         1  LCD data sampled on falling edge of L_PCLK
LCCR3_OEP                         0  LCD L_BIAS output enable active low
LCCR3_BPP                         8  LCD bits per pixel
LCCR3_DPC                         0  LCD double pixel clock rate at L_PCLK