Hi Bill,
This is a couple of days of work. Your starting point is the TI OMAP technical reference manual (Rev. B). In it you will find the OMAP signals. The Overo J1 and J4 connectors expose some of the signals. In the TRM document, you will find how to set the multiplexing modes for each of the pins.

For example, I am working on the GPMC interface, which is exposed through the J4 connectors. These are prefixed as gpmc_xxx in the TRM, and EM_xxx on the Overo J4 connector description. 

Next read the section on Pad functional multiplexing, which tells you how to configure each pad, so that you get the signals that you need. There are also some tables that list which signals are available for the various modes. 

Here is an example workflow. This is a work in progress! :-)


How to reconfigure the TI OMAP's pad multiplexing option to mode 1.

a. Configure pad gpmc_ncs3 to sys_ndmareq0 in mode 1. The register name is CONTROL_PADCONF_GPMC_NCS3[15:0]. The physical address is 0x4800 20B4.

b. Configure pad gpmc_ncs7 to gpmc_io_dir in mode 1. The register name is CONTROL_PADCONF_GPMC_NCS7[15:0]. The physical address is 0x4800 20BC.


Solution: 

Refer section 7.5.4 Pad Configuration Programming Points, page 899 of the TI OMAP 35xx TRM (Rev. B).

Step 01: Set the signal direction for the pin. 

sys_ndmareq0

sys_ndmareq0 is an input signal, see Table 7-4 of the TI OMAP 35xx TRM (Rev. B).

In order to configure the pin to input only mode, set the INPUTENABLE (1 bit) of the CONTROL_PADCONF_GPMC_NCS3[15:0] pad configuration register to 1. 

The location of the INPUTENABLE bit for the CONTROL_PADCONF_GPMC_NCS3[15:0] pad configuration register corresponds to bit 8.

gpmc_io_dir

gpmc_io_dir is an output signal, see Table 1: GPMC I/O Description. 

In order to configure the pin to output only mode, set the INPUTENABLE (1 bit) of the CONTROL_PADCONF_GPMC_NCS7[15:0] pad configuration register to 0. 

The location of the INPUTENABLE bit for the CONTROL_PADCONF_GPMC_NCS7[15:0] pad configuration register corresponds to bit 8.


Step 02: Set the multiplexing mode for the pin.

Table 7-4 Core Control Module Pad Configuration Register Fields, of the TI OMAP 35xx TRM (Rev. B). shows that the sys_ndmareq0 and gpmc_io_dir signals are available in Mode 1.

In order to configure the pin multiplexing mode to Mode 1, set the MUXMODE (3 bits) of the pad configuration register to 0b001. 

For both CONTROL_PADCONF_GPMC_NCS3[15:0] and CONTROL_PADCONF_GPMC_NCS7[15:0], the MUXMODE bits corresponds to bits 2 downto 0.


Step 03: Configure the pull of the pad when you use it as input. 

sys_ndmareq0

sys_ndmareq0 is an input signal and we need to configure the pull of the pad.

TODO: Should you enable pull-up or pull-down for the sys_ndmareq0 pin? If yes, you will have to set the PULL (2 bits) of the pad configuration register. See page 901 for more information of the TI OMAP 35xx TRM (Rev. B). 

The following notes give additional explanations about the pin configuration:

1. In order to avoid unconnected pins, the configuration depends on its use:
If the pin is not driven externally, a pull up/down is required.
Otherwise, a pull up/down is not necessary.

2. Pull conflicts occur when there are different pulls on the same line. In order to correctly configure the pin, avoid external and internal pull together.

3. Logic conflicts consist in different electrical levels at the same time on one line. This can occur when
several devices are connected to the same line. The two possible cases are:
If no external device drives the line, configure the pin to drive a '0'.
If another device drives the line, either the same value has to be driven or the pin has to be disconnected (HZ).


To enable pull-up, write 0b1 in the PULLTYPESELECT bit and 0b1 in the PULLUDENABLE bit of the corresponding pad configuration register.

To enable pull-down, write 0b0 in the PULLTYPESELECT bit and 0b1 in the PULLUDENABLE bit of the corresponding pad configuration register.

Note: When a pad is configured as output, the pull is automatically disabled.

Step 04: Set the sensitivity on the sys_ndmareq[6:0] input pins

The seven SYS_NDMAREQ0 to SYS_NDMAREQ6 input pins can be either level or edge sensitive.
SENSDMAREQ0 bit CONTROL.CONTROL_DEVCONF0[0]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ1 bit CONTROL.CONTROL_DEVCONF0[1]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ2 bit CONTROL.CONTROL_DEVCONF1[7]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ3 bit CONTROL.CONTROL_DEVCONF1[8]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ4 bit CONTROL.CONTROL_DEVCONF1[21]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ5 bit CONTROL.CONTROL_DEVCONF1[22]:
0: Level sensitivity
1: Edge sensitivity

SENSDMAREQ6 bit CONTROL.CONTROL_DEVCONF1[23]:
0: Level sensitivity
1: Edge sensitivity

For more details on DMA, see the DMA chapter.

Step 05: Set the GPMC I/O drive strength for the pin.

GPMC_NCS3 bit CONTROL.CONTROL_PROG_IO0[11] selects GPMC_NCS3 I/O drive strength
0: Load range = [2pf : 6pf]
1: Load range = [6pf : 12pf]

GPMC_NCS7 bit CONTROL.CONTROL_PROG_IO0[7] selects GPMC_NCS7 I/O drive strength
0: Load range = [2pf : 6pf]
1: Load range = [6pf : 12pf]


Best regards,

Elvis






On Mar 26, 2009, at 2:57 AM, Bill West wrote:

Hi,

I am designing in the two 70 pin connectors to provide future expansion for an existing AT91SAM7X board for an embed application.  It's hard for me to tell from the existing documentation how the J1 and J4 connectors map to the OMAP CBB chip.  A table with that mapping would help.  (Or if I could know which I/O mode the OMAP is in for the J1 and J4 reverences provided on the website.)

I need the following resources to replace what I'm using on the ARM7:

2 Async serial interfaces (RS-485)
2 SPI with CS's
40 GPIO

Thanks in advance, Bill
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