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#161 PIC Enhanced Midrange Core ADDFSR Bug Report

Roy Rankin
Scott Dattalo

Posted on behalf of Tim Burke timburke@alumni.rice.edu


I started using gpsim 0.27.0 to simulate the pic12f1822 processor, which has an enhanced midrange core. The goal is to use gpsim for automated unit tests on embedded code that I’m developing for that processor. I ran in to what I think are two bugs in the implementation of the ADDFSR instruction. I have fixed them both and would like to submit the change after discussion to make sure that I haven’t missed something. The bugs are:

  1. Issue: ADDFSR instruction is not added to the op_16ext table in 14bit-hexdecode.cc so ADDFSR instructions are never correctly decoded and instead are processed as movlw instructions.
    Fix: Add entry to op_16ext to process ADDFSR instruction and remove movlw entry in op_16cxx that corresponded to that opcode

  2. Issue: ADDFSR::execute improperly discards the high nibble of FSR{0,1}H when incrementing because it calls get_fsr_value() which returns far & 0xFFF, zeroing out the high nibble. This is incorrect because when the FSR register is pointing at program rom, the high order bit will be set, meaning that ADDFSR does not work when pointing to program ram
    Fix: Rewrite 14bit-instructions.cc:73 to use ia->fsr_value rather than get_fsr_value() in order to preserve all bits of FSRH.

I have implemented the above fixes and am using them currently. I just wanted to check and see if there was a reason this was not implemented before submitting a bug report and patch.

Thank you very much for your time and a great program!

Tim Burke


  • Roy Rankin
    Roy Rankin

    • status: open --> closed-fixed
    • assigned_to: Roy Rankin
    • Group: -->


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