Learn how easy it is to sync an existing GitHub or Google Code repo to a SourceForge project! See Demo

Close

[1272ff]: ilg.gnuarmeclipse.templates.stm / templates / micro-os-plus / stm32f4-hal.pack / src / stm32f4-hal / stm32f4xx_hal_i2s.c Maximize Restore History

Download this file

stm32f4xx_hal_i2s.c    1683 lines (1462 with data), 55.2 kB

   1
   2
   3
   4
   5
   6
   7
   8
   9
  10
  11
  12
  13
  14
  15
  16
  17
  18
  19
  20
  21
  22
  23
  24
  25
  26
  27
  28
  29
  30
  31
  32
  33
  34
  35
  36
  37
  38
  39
  40
  41
  42
  43
  44
  45
  46
  47
  48
  49
  50
  51
  52
  53
  54
  55
  56
  57
  58
  59
  60
  61
  62
  63
  64
  65
  66
  67
  68
  69
  70
  71
  72
  73
  74
  75
  76
  77
  78
  79
  80
  81
  82
  83
  84
  85
  86
  87
  88
  89
  90
  91
  92
  93
  94
  95
  96
  97
  98
  99
 100
 101
 102
 103
 104
 105
 106
 107
 108
 109
 110
 111
 112
 113
 114
 115
 116
 117
 118
 119
 120
 121
 122
 123
 124
 125
 126
 127
 128
 129
 130
 131
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148
 149
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160
 161
 162
 163
 164
 165
 166
 167
 168
 169
 170
 171
 172
 173
 174
 175
 176
 177
 178
 179
 180
 181
 182
 183
 184
 185
 186
 187
 188
 189
 190
 191
 192
 193
 194
 195
 196
 197
 198
 199
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213
 214
 215
 216
 217
 218
 219
 220
 221
 222
 223
 224
 225
 226
 227
 228
 229
 230
 231
 232
 233
 234
 235
 236
 237
 238
 239
 240
 241
 242
 243
 244
 245
 246
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285
 286
 287
 288
 289
 290
 291
 292
 293
 294
 295
 296
 297
 298
 299
 300
 301
 302
 303
 304
 305
 306
 307
 308
 309
 310
 311
 312
 313
 314
 315
 316
 317
 318
 319
 320
 321
 322
 323
 324
 325
 326
 327
 328
 329
 330
 331
 332
 333
 334
 335
 336
 337
 338
 339
 340
 341
 342
 343
 344
 345
 346
 347
 348
 349
 350
 351
 352
 353
 354
 355
 356
 357
 358
 359
 360
 361
 362
 363
 364
 365
 366
 367
 368
 369
 370
 371
 372
 373
 374
 375
 376
 377
 378
 379
 380
 381
 382
 383
 384
 385
 386
 387
 388
 389
 390
 391
 392
 393
 394
 395
 396
 397
 398
 399
 400
 401
 402
 403
 404
 405
 406
 407
 408
 409
 410
 411
 412
 413
 414
 415
 416
 417
 418
 419
 420
 421
 422
 423
 424
 425
 426
 427
 428
 429
 430
 431
 432
 433
 434
 435
 436
 437
 438
 439
 440
 441
 442
 443
 444
 445
 446
 447
 448
 449
 450
 451
 452
 453
 454
 455
 456
 457
 458
 459
 460
 461
 462
 463
 464
 465
 466
 467
 468
 469
 470
 471
 472
 473
 474
 475
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494
 495
 496
 497
 498
 499
 500
 501
 502
 503
 504
 505
 506
 507
 508
 509
 510
 511
 512
 513
 514
 515
 516
 517
 518
 519
 520
 521
 522
 523
 524
 525
 526
 527
 528
 529
 530
 531
 532
 533
 534
 535
 536
 537
 538
 539
 540
 541
 542
 543
 544
 545
 546
 547
 548
 549
 550
 551
 552
 553
 554
 555
 556
 557
 558
 559
 560
 561
 562
 563
 564
 565
 566
 567
 568
 569
 570
 571
 572
 573
 574
 575
 576
 577
 578
 579
 580
 581
 582
 583
 584
 585
 586
 587
 588
 589
 590
 591
 592
 593
 594
 595
 596
 597
 598
 599
 600
 601
 602
 603
 604
 605
 606
 607
 608
 609
 610
 611
 612
 613
 614
 615
 616
 617
 618
 619
 620
 621
 622
 623
 624
 625
 626
 627
 628
 629
 630
 631
 632
 633
 634
 635
 636
 637
 638
 639
 640
 641
 642
 643
 644
 645
 646
 647
 648
 649
 650
 651
 652
 653
 654
 655
 656
 657
 658
 659
 660
 661
 662
 663
 664
 665
 666
 667
 668
 669
 670
 671
 672
 673
 674
 675
 676
 677
 678
 679
 680
 681
 682
 683
 684
 685
 686
 687
 688
 689
 690
 691
 692
 693
 694
 695
 696
 697
 698
 699
 700
 701
 702
 703
 704
 705
 706
 707
 708
 709
 710
 711
 712
 713
 714
 715
 716
 717
 718
 719
 720
 721
 722
 723
 724
 725
 726
 727
 728
 729
 730
 731
 732
 733
 734
 735
 736
 737
 738
 739
 740
 741
 742
 743
 744
 745
 746
 747
 748
 749
 750
 751
 752
 753
 754
 755
 756
 757
 758
 759
 760
 761
 762
 763
 764
 765
 766
 767
 768
 769
 770
 771
 772
 773
 774
 775
 776
 777
 778
 779
 780
 781
 782
 783
 784
 785
 786
 787
 788
 789
 790
 791
 792
 793
 794
 795
 796
 797
 798
 799
 800
 801
 802
 803
 804
 805
 806
 807
 808
 809
 810
 811
 812
 813
 814
 815
 816
 817
 818
 819
 820
 821
 822
 823
 824
 825
 826
 827
 828
 829
 830
 831
 832
 833
 834
 835
 836
 837
 838
 839
 840
 841
 842
 843
 844
 845
 846
 847
 848
 849
 850
 851
 852
 853
 854
 855
 856
 857
 858
 859
 860
 861
 862
 863
 864
 865
 866
 867
 868
 869
 870
 871
 872
 873
 874
 875
 876
 877
 878
 879
 880
 881
 882
 883
 884
 885
 886
 887
 888
 889
 890
 891
 892
 893
 894
 895
 896
 897
 898
 899
 900
 901
 902
 903
 904
 905
 906
 907
 908
 909
 910
 911
 912
 913
 914
 915
 916
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930
 931
 932
 933
 934
 935
 936
 937
 938
 939
 940
 941
 942
 943
 944
 945
 946
 947
 948
 949
 950
 951
 952
 953
 954
 955
 956
 957
 958
 959
 960
 961
 962
 963
 964
 965
 966
 967
 968
 969
 970
 971
 972
 973
 974
 975
 976
 977
 978
 979
 980
 981
 982
 983
 984
 985
 986
 987
 988
 989
 990
 991
 992
 993
 994
 995
 996
 997
 998
 999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
/**
******************************************************************************
* @file stm32f4xx_hal_i2s.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-February-2014
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The I2S HAL driver can be used as follow:
(#) Declare a I2S_HandleTypeDef handle structure.
(#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
(##) Enable the SPIx interface clock.
(##) I2S pins configuration:
(+++) Enable the clock for the I2S GPIOs.
(+++) Configure these I2S pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
and HAL_I2S_Receive_IT() APIs).
(+++) Configure the I2Sx interrupt priority.
(+++) Enable the NVIC I2S IRQ handle.
(##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
and HAL_I2S_Receive_DMA() APIs:
(+++) Declare a DMA handle structure for the Tx/Rx stream.
(+++) Enable the DMAx interface clock.
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx Stream.
(+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
DMA Tx/Rx Stream.
(#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
using HAL_I2S_Init() function.
-@- The specific I2S interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process.
-@- Make sure that either:
(+@) I2S PLL is configured or
(+@) External clock source is configured after setting correctly
the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file.
(#) Three mode of operations are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
(+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
(+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
*** DMA mode IO operation ***
==============================
[..]
(+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
(+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
(+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_TxCpltCallback
(+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
(+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
(+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
add his own code by customization of function pointer HAL_I2S_RxCpltCallback
(+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_I2S_ErrorCallback
(+) Pause the DMA Transfer using HAL_I2S_DMAPause()
(+) Resume the DMA Transfer using HAL_I2S_DMAResume()
(+) Stop the DMA Transfer using HAL_I2S_DMAStop()
*** I2S HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in USART HAL driver.
(+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
(+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
(+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
(+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
[..]
(@) You can refer to the I2S HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
/** @defgroup I2S
* @brief I2S HAL module driver
* @{
*/
#ifdef HAL_I2S_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2S_Private_Functions
* @{
*/
/** @defgroup I2S_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This subsection provides a set of functions allowing to initialize and
de-initialiaze the I2Sx peripheral in simplex mode:
(+) User must Implement HAL_I2S_MspInit() function in which he configures
all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
(+) Call the function HAL_I2S_Init() to configure the selected device with
the selected configuration:
(++) Mode
(++) Standard
(++) Data Format
(++) MCLK Output
(++) Audio frequency
(++) Polarity
(++) Full duplex mode
(+) Call the function HAL_I2S_DeInit() to restore the default configuration
of the selected I2Sx periperal.
@endverbatim
* @{
*/
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
* @param hi2s: I2S handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
{
uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0, i2sclk = 0;
/* Check the I2S handle allocation */
if(hi2s == NULL)
{
return HAL_ERROR;
}
/* Check the I2S parameters */
assert_param(IS_I2S_MODE(hi2s->Init.Mode));
assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource));
assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode));
if(hi2s->State == HAL_I2S_STATE_RESET)
{
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2S_MspInit(hi2s);
}
hi2s->State = HAL_I2S_STATE_BUSY;
/*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
hi2s->Instance->I2SPR = 0x0002;
/* Get the I2SCFGR register value */
tmpreg = hi2s->Instance->I2SCFGR;
/* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */
/* If the requested audio frequency is not the default, compute the prescaler */
if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
{
/* Check the frame length (For the Prescaler computing) *******************/
if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
{
/* Packet length is 32 bits */
packetlength = 2;
}
/* Get I2S source Clock frequency ****************************************/
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f4xx_conf.h file */
if(hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL)
{
/* Set external clock as I2S clock source */
if((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
{
RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
}
/* Set the I2S clock to the external clock value */
i2sclk = EXTERNAL_CLOCK_VALUE;
}
else
{
/* Check if PLLI2S is enabled or Not */
if((RCC->CR & RCC_CR_PLLI2SON) != RCC_CR_PLLI2SON)
{
hi2s->State= HAL_I2S_STATE_READY;
return HAL_ERROR;
}
/* Set PLLI2S as I2S clock source */
if((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
{
RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
}
/* Get the PLLM value */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
{
/* Get the I2S source clock value */
i2sclk = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
else
{
/* Get the I2S source clock value */
i2sclk = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
i2sclk *= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & (RCC_PLLI2SCFGR_PLLI2SN >> 6));
i2sclk /= (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & (RCC_PLLI2SCFGR_PLLI2SR >> 28));
}
/* Compute the Real divider depending on the MCLK output state, with a floating point */
if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
{
/* MCLK output is enabled */
tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
}
else
{
/* MCLK output is disabled */
tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
}
/* Remove the flatting point */
tmp = tmp / 10;
/* Check the parity of the divider */
i2sodd = (uint32_t)(tmp & (uint32_t)1);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint32_t) (i2sodd << 8);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if((i2sdiv < 2) || (i2sdiv > 0xFF))
{
/* Set the default values */
i2sdiv = 2;
i2sodd = 0;
}
/* Write to SPIx I2SPR register the computed value */
hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
/* Configure the I2S with the I2S_InitStruct values */
tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
/* Write to SPIx I2SCFGR */
hi2s->Instance->I2SCFGR = tmpreg;
/* Configure the I2S extended if the full duplex mode is enabled */
if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
/* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
I2SxEXT(hi2s->Instance)->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD);
I2SxEXT(hi2s->Instance)->I2SPR = 2;
/* Get the I2SCFGR register value */
tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR;
/* Get the mode to be configured for the extended I2S */
if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX))
{
tmp = I2S_MODE_SLAVE_RX;
}
else
{
if((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX))
{
tmp = I2S_MODE_SLAVE_TX;
}
}
/* Configure the I2S Slave with the I2S Master parameter values */
tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | tmp | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL);
/* Write to SPIx I2SCFGR */
I2SxEXT(hi2s->Instance)->I2SCFGR = tmpreg;
}
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the I2S peripheral
* @param hi2s: I2S handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
{
/* Check the I2S handle allocation */
if(hi2s == NULL)
{
return HAL_ERROR;
}
hi2s->State = HAL_I2S_STATE_BUSY;
/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
HAL_I2S_MspDeInit(hi2s);
hi2s->State = HAL_I2S_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
/**
* @brief I2S MSP Init
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspInit could be implenetd in the user file
*/
}
/**
* @brief I2S MSP DeInit
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_MspDeInit could be implenetd in the user file
*/
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/**
* @}
*/
/** @defgroup I2S_Group2 IO operation functions
* @brief Data transfers functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the I2S data
transfers.
(#) There is two mode of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
The end of the data processing will be indicated through the
dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
(#) Blocking mode functions are :
(++) HAL_I2S_Transmit()
(++) HAL_I2S_Receive()
(#) No-Blocking mode functions with Interrupt are :
(++) HAL_I2S_Transmit_IT()
(++) HAL_I2S_Receive_IT()
(#) No-Blocking mode functions with DMA are :
(++) HAL_I2S_Transmit_DMA()
(++) HAL_I2S_Receive_DMA()
(#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
(++) HAL_I2S_TxCpltCallback()
(++) HAL_I2S_RxCpltCallback()
(++) HAL_I2S_ErrorCallback()
@endverbatim
* @{
*/
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wconversion"
#endif
/**
* @brief Transmit an amount of data in blocking mode
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @param Timeout: Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmp1 = 0, tmp2 = 0;
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
if(hi2s->State == HAL_I2S_STATE_READY)
{
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_TX;
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
while(hi2s->TxXferCount > 0)
{
hi2s->Instance->DR = (*pData++);
hi2s->TxXferCount--;
/* Wait until TXE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
}
/* Wait until Busy flag is reset */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in blocking mode
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @param Timeout: Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
* in continouse way and as the I2S is not disabled at the end of the I2S transaction.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tmp1 = 0, tmp2 = 0;
if((pData == NULL ) || (Size == 0))
{
return HAL_ERROR;
}
if(hi2s->State == HAL_I2S_STATE_READY)
{
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_RX;
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
/* Receive data */
while(hi2s->RxXferCount > 0)
{
/* Wait until RXNE flag is set */
if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
(*pData++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
}
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmp1 = 0, tmp2 = 0;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
hi2s->pTxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation
* between Master and Slave otherwise the I2S interrupt should be optimized.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t tmp1 = 0, tmp2 = 0;
if(hi2s->State == HAL_I2S_STATE_READY)
{
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
hi2s->pRxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)||\
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Enable TXE and ERR interrupt */
__HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to the Transmit data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t *tmp;
uint32_t tmp1 = 0, tmp2 = 0;
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
if(hi2s->State == HAL_I2S_STATE_READY)
{
hi2s->pTxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->TxXferSize = Size*2;
hi2s->TxXferCount = Size*2;
}
else
{
hi2s->TxXferSize = Size;
hi2s->TxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_TX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Set the I2S Tx DMA Half transfert complete callback */
hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
/* Set the I2S Tx DMA transfert complete callback */
hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
/* Set the DMA error callback */
hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
/* Enable the Tx DMA Stream */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Check if the I2S Tx request is already enabled */
if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
{
/* Enable Tx DMA Request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Receive an amount of data in non-blocking mode with DMA
* @param hi2s: I2S handle
* @param pData: a 16-bit pointer to the Receive data buffer.
* @param Size: number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
{
uint32_t *tmp;
uint32_t tmp1 = 0, tmp2 = 0;
if((pData == NULL) || (Size == 0))
{
return HAL_ERROR;
}
if(hi2s->State == HAL_I2S_STATE_READY)
{
hi2s->pRxBuffPtr = pData;
tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
if((tmp1 == I2S_DATAFORMAT_24B)|| \
(tmp2 == I2S_DATAFORMAT_32B))
{
hi2s->RxXferSize = Size*2;
hi2s->RxXferCount = Size*2;
}
else
{
hi2s->RxXferSize = Size;
hi2s->RxXferCount = Size;
}
/* Process Locked */
__HAL_LOCK(hi2s);
hi2s->State = HAL_I2S_STATE_BUSY_RX;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
/* Set the I2S Rx DMA Half transfert complete callback */
hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
/* Set the I2S Rx DMA transfert complete callback */
hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
/* Set the DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
/* Enable the Rx DMA Stream */
tmp = (uint32_t*)&pData;
HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
/* Check if the I2S is already enabled */
if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Check if the I2S Rx request is already enabled */
if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
{
/* Enable Rx DMA Request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/**
* @brief Pauses the audio stream playing from the Media.
* @param hi2s: I2S handle
* @retval None
*/
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Disable the I2S DMA Tx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Disable the I2S DMA Rx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
{
/* Disable the I2S DMA Tx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
/* Disable the I2SEx Rx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
else
{
/* Disable the I2S DMA Rx request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
/* Disable the I2SEx Tx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Resumes the audio stream playing from the Media.
* @param hi2s: I2S handle
* @retval None
*/
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Enable the I2S DMA Tx request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Enable the I2S DMA Rx request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
}
else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if((hi2s->Init.Mode == I2S_MODE_SLAVE_TX)||(hi2s->Init.Mode == I2S_MODE_MASTER_TX))
{
/* Enable the I2S DMA Tx request */
hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
/* Disable the I2SEx Rx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
}
else
{
/* Enable the I2S DMA Rx request */
hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
/* Enable the I2SEx Tx DMA Request */
I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
}
}
/* If the I2S peripheral is still not enabled, enable it */
if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
{
/* Enable I2S peripheral */
__HAL_I2S_ENABLE(hi2s);
}
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief Resumes the audio stream playing from the Media.
* @param hi2s: I2S handle
* @retval None
*/
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
{
/* Process Locked */
__HAL_LOCK(hi2s);
/* Disable the I2S Tx/Rx DMA requests */
hi2s->Instance->CR2 &= ~SPI_CR2_TXDMAEN;
hi2s->Instance->CR2 &= ~SPI_CR2_RXDMAEN;
if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
/* Disable the I2S extended Tx/Rx DMA requests */
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
/* Abort the I2S DMA Stream tx */
if(hi2s->hdmatx != NULL)
{
HAL_DMA_Abort(hi2s->hdmatx);
}
/* Abort the I2S DMA Stream rx */
if(hi2s->hdmarx != NULL)
{
HAL_DMA_Abort(hi2s->hdmarx);
}
/* Disable I2S peripheral */
__HAL_I2S_DISABLE(hi2s);
if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
/* Disable the I2Sext peripheral */
I2SxEXT(hi2s->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE;
}
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_OK;
}
/**
* @brief This function handles I2S interrupt request.
* @param hi2s: I2S handle
* @retval HAL status
*/
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
{
uint32_t tmp1 = 0, tmp2 = 0;
if(hi2s->Init.FullDuplexMode != I2S_FULLDUPLEXMODE_ENABLE)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
/* I2S in mode Receiver ------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
I2S_Receive_IT(hi2s);
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
/* I2S Overrun error interrupt occured ---------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
}
}
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
/* I2S in mode Tramitter -----------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
I2S_Transmit_IT(hi2s);
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
/* I2S Underrun error interrupt occured --------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
}
}
}
else
{
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_RXNE;
/* I2Sext in mode Receiver ---------------------------------------------*/
if((tmp1 == SPI_SR_RXNE) && (tmp2 == I2S_IT_RXNE))
{
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2Sext RXNE interrupt will be generated to manage the full-duplex receive phase. */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
I2SEx_TransmitReceive_IT(hi2s);
}
}
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_OVR;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
/* I2Sext Overrun error interrupt occured ------------------------------*/
if((tmp1 == SPI_SR_OVR) && (tmp2 == I2S_IT_ERR))
{
/* Clear I2Sext OVR Flag */
I2SxEXT(hi2s->Instance)->DR;
I2SxEXT(hi2s->Instance)->SR;
hi2s->ErrorCode |= HAL_I2SEX_ERROR_OVR;
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE);
/* I2S in mode Tramitter -----------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* When the I2S mode is configured as I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX,
the I2S TXE interrupt will be generated to manage the full-duplex transmit phase. */
if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
{
I2SEx_TransmitReceive_IT(hi2s);
}
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
/* I2S Underrun error interrupt occured --------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_UDRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_UDR;
}
}
/* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
else
{
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE);
/* I2S in mode Receiver ------------------------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2S RXNE interrupt will be generated to manage the full-duplex receive phase. */
if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
{
I2SEx_TransmitReceive_IT(hi2s);
}
}
tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR);
tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR);
/* I2S Overrun error interrupt occured ---------------------------------*/
if((tmp1 != RESET) && (tmp2 != RESET))
{
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
hi2s->ErrorCode |= HAL_I2S_ERROR_OVR;
}
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_TXE;
/* I2Sext in mode Tramitter --------------------------------------------*/
if((tmp1 == SPI_SR_TXE) && (tmp2 == I2S_IT_TXE))
{
tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
/* When the I2S mode is configured as I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX,
the I2Sext TXE interrupt will be generated to manage the full-duplex transmit phase. */
if((tmp1 == I2S_MODE_MASTER_RX) || (tmp2 == I2S_MODE_SLAVE_RX))
{
I2SEx_TransmitReceive_IT(hi2s);
}
}
tmp1 = I2SxEXT(hi2s->Instance)->SR & SPI_SR_UDR;
tmp2 = I2SxEXT(hi2s->Instance)->CR2 & I2S_IT_ERR;
/* I2Sext Underrun error interrupt occured -----------------------------*/
if((tmp1 == SPI_SR_UDR) && (tmp2 == I2S_IT_ERR))
{
/* Clear I2Sext UDR Flag */
I2SxEXT(hi2s->Instance)->SR;
hi2s->ErrorCode |= HAL_I2SEX_ERROR_UDR;
}
}
}
/* Call the Error call Back in case of Errors */
if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE)
{
/* Set the I2S state ready to be able to start again the process */
hi2s->State= HAL_I2S_STATE_READY;
HAL_I2S_ErrorCallback(hi2s);
}
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wunused-parameter"
#endif
/**
* @brief Tx Transfer Half completed callbacks
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file
*/
}
/**
* @brief Tx Transfer completed callbacks
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_TxCpltCallback could be implenetd in the user file
*/
}
/**
* @brief Rx Transfer half completed callbacks
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implenetd in the user file
*/
}
/**
* @brief Rx Transfer completed callbacks
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_RxCpltCallback could be implenetd in the user file
*/
}
/**
* @brief I2S error callbacks
* @param hi2s: I2S handle
* @retval None
*/
__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_I2S_ErrorCallback could be implenetd in the user file
*/
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/**
* @}
*/
/** @defgroup I2S_Group3 Peripheral State and Errors functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection permit to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the I2S state
* @param hi2s : I2S handle
* @retval HAL state
*/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
{
return hi2s->State;
}
/**
* @brief Return the I2S error code
* @param hi2s : I2S handle
* @retval I2S Error Code
*/
HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
{
return hi2s->ErrorCode;
}
/**
* @}
*/
/**
* @brief DMA I2S transmit process complete callback
* @param hdma : DMA handle
* @retval None
*/
void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
hi2s->TxXferCount = 0;
/* Disable Tx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
/* Disable Rx DMA Request for the slave*/
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
}
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if(hi2s->RxXferCount == 0)
{
hi2s->State = HAL_I2S_STATE_READY;
}
}
else
{
hi2s->State = HAL_I2S_STATE_READY;
}
}
HAL_I2S_TxCpltCallback(hi2s);
}
/**
* @brief DMA I2S transmit process half complete callback
* @param hdma : DMA handle
* @retval None
*/
void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
HAL_I2S_TxHalfCpltCallback(hi2s);
}
/**
* @brief DMA I2S receive process complete callback
* @param hdma : DMA handle
* @retval None
*/
void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
{
/* Disable Rx DMA Request */
hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE)
{
/* Disable Tx DMA Request for the slave*/
I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
}
hi2s->RxXferCount = 0;
if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
{
if(hi2s->TxXferCount == 0)
{
hi2s->State = HAL_I2S_STATE_READY;
}
}
else
{
hi2s->State = HAL_I2S_STATE_READY;
}
}
HAL_I2S_RxCpltCallback(hi2s);
}
/**
* @brief DMA I2S receive process half complete callback
* @param hdma : DMA handle
* @retval None
*/
void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
HAL_I2S_RxHalfCpltCallback(hi2s);
}
/**
* @brief DMA I2S communication error callback
* @param hdma : DMA handle
* @retval None
*/
void I2S_DMAError(DMA_HandleTypeDef *hdma)
{
I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
hi2s->TxXferCount = 0;
hi2s->RxXferCount = 0;
hi2s->State= HAL_I2S_STATE_READY;
hi2s->ErrorCode |= HAL_I2S_ERROR_DMA;
HAL_I2S_ErrorCallback(hi2s);
}
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
* @param hi2s: I2S handle
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
{
/* Process Locked */
__HAL_LOCK(hi2s);
/* Transmit data */
hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
hi2s->TxXferCount--;
if(hi2s->TxXferCount == 0)
{
/* Disable TXE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
HAL_I2S_TxCpltCallback(hi2s);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wconversion"
#endif
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
* @param hi2s: I2S handle
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
{
if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
{
/* Process Locked */
__HAL_LOCK(hi2s);
/* Receive data */
(*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
hi2s->RxXferCount--;
/* Check if Master Receiver mode is selected */
if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
{
/* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
access to the SPI_SR register. */
__HAL_I2S_CLEAR_OVRFLAG(hi2s);
}
if(hi2s->RxXferCount == 0)
{
/* Disable RXNE and ERR interrupt */
__HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE | I2S_IT_ERR);
hi2s->State = HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
HAL_I2S_RxCpltCallback(hi2s);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
}
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
// [ILG]
#if defined ( __GNUC__ )
#pragma GCC diagnostic pop
#endif
/**
* @brief This function handles I2S Communication Timeout.
* @param hi2s: I2S handle
* @param Flag: Flag checked
* @param State: Value of the flag expected
* @param Timeout: Duration of the timeout
* @retval HAL status
*/
HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
{
uint32_t timeout = 0;
timeout = HAL_GetTick() + Timeout;
/* Wait until flag is set */
if(Status == RESET)
{
while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
if(HAL_GetTick() >= timeout)
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_TIMEOUT;
}
}
}
}
else
{
while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
if(HAL_GetTick() >= timeout)
{
/* Set the I2S State ready */
hi2s->State= HAL_I2S_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2s);
return HAL_TIMEOUT;
}
}
}
}
return HAL_OK;
}
/**
* @}
*/
#endif /* HAL_I2S_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/