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I'm fairly new to the Cortex M3 assembly language, but also new to FreeRTOS and was having a look at the function:
void vPortStartFirstTask( void )
" ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
" ldr r0, \n"
" ldr r0, \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */
" cpsie i \n" /* Globally enable interrupts. */
" svc 0 \n" /* System call to start first task. */
" nop \n"
I liked the idea of using the vector table location to grab the original stack location (and plan to use this in my fault handlers to try and set the stack back to something useful).
I'm wondering why is read twice in this function. Is that a typo? Or was there a purpose? Because I'm learning the assembly language and processor, this line confused me and I'm just wondering if there's a subtle point about the processor I'm missing that might require the memory to be read twice (or some timing thing going on).
Second question (or maybe this is just a comment) is about the "cpsie i" instruction. I was surprised to find out that the default for this bit is that interrupts are enabled. (Most processors come up with interrupts blocked, and it surprised me that i and f are both unmasked). All the ports I took a look at set this even though it appears the power-on default is enabled for this bit and it's not needed (unless, I suppose, some user code might have disabled it early on).
Finally, the comments that goes along with the functions __enable_fault_irq() and __disable_fault_irq() (which enable/disable the FAULTMASK) I found are probably cut/paste errors from another Arm port perhaps? The comments mention FIQ, which the Cortex doesn't have but as I remember other Arm processors do have.
Minor issues, but as I'm new and learning, I was interested in seeing if I have something wrong.
I realize now why there are two "ldr r0, "
It's kind of obvious if I'd thought about it longer.
Calling FreeRTOS API functions before the scheduler has started will deliberately leave interrupts disabled to make sure interrupts don't use the scheduler functionality before it is ready. It does not use the global interrupt mask though, only basepri. Calling SVC with global interrupts disabled will cause a fault though, so I guess the cpsie instruction just ensures the application or start up code has not disabled interrupts before it calls svc.