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Commit [e36891] Maximize Restore History

Finished PLL/clocks configuration by the RBL register setup

Andrey Filippov Andrey Filippov 2013-09-15

changed ezynq_clk.py
changed ezynq_clkcfg_defs.py
changed ezynq_ddr.py
changed ezynq_slcr_clk_def.py
changed ezynqcfg.py
changed test.mk
ezynq_clk.py Diff Switch to side-by-side view
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ezynq_clkcfg_defs.py Diff Switch to side-by-side view
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ezynq_ddr.py Diff Switch to side-by-side view
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ezynq_slcr_clk_def.py Diff Switch to side-by-side view
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ezynqcfg.py Diff Switch to side-by-side view
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test.mk Diff Switch to side-by-side view
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