RE: [Dri-devel] caching, writecombining, framebuffers, agp

[Jeff H. <Wa...@ad...>]

This really really sounds like a read cache problem, I saw similar behavior
before.  I think on the Matrox cards, but my memory is abit fuzzy.  Can you
try writing to two different locations (a least several K apart), then
reading your values?

I would recommend trying something like the following pseudocode:
{
	Sync the dma stream and wait for drawing completion
	Read from the very last pixel in the framebuffer, write its value back.
	Read from the very first pixel in the framebuffer, write its value back.
	Do your normal operations.
}

If this fixes the problem you will have to reserve a pixel somewhere that
can be destroyed.  I believe the first read/modify/write could get the wrong
pixel value, but the second should work.

Read caches can sometimes be really weird, and might have very stale values
sometimes.

Oah, I think the reason the mtrr's aren't getting turned off properly is
because the Xserver disable code doesn't probably take into account the fact
that the drm kernel module sets up mtrr's as well.  This sort of thing needs
to be handled in the DRI Initialization code in the Xserver.  Its probably
telling the kernel module to create the mtrr region.

Hope this approach helps, it will probably at least give you an idea if its
a read cache problem.

-Jeff