On 1/15/07, Dave Airlie <firstname.lastname@example.org
> I did a little more digging on this. It really looks like the address of "
> ring.start" is completely different than what is in RADEON_CP_RB_BASE. (I
> realize that ring.start
is a virtual address and RADEON_CP_RB_BASE is a bus
> address. However, the drmAddMap call in RADEONDRIPciInit sets the address
> to 0, so I don't think it is setting 0x5800000 properly either...)
> In any event, I think that the radeon DRM module and the card have a
> completely different idea of where the ringbuffer is. (And as a result the
> card is executing crap....)
> I'm off to find out how all of those mappings work... (I also am going to
> strace the fglrx driver to see how it sets them up...)
I've looked at one of these laptops yesterday (thanks mjg59...) and I
thought it might be possible to get PCI GART working on it, I didn't get
it working, but I think it might be an initial method.. I'm hoping to get
some time later in the week to look at it again..
Since you obviously understand how the GART fits in, I have some questions. ;-)
I've been reading through code and googling, but I haven't been able to
find a clear explanation about how you actually USE the gart.
Are these the right steps for using a GART?
1) Allocate as many host pages as the GART can map.
2) Fill in the GART table with the physical addresses of the pages that you just allocated.
3) Tell the card the bus address of the GART table
4) Tell the card about the lower/upper address of the vm which should be remapped.
(This is the same view of memory that the process has...)
5) Write stuff to dev_priv->gart_vm_start (from the process's point of view), and the graphics card will be able to retrieve it at the same address.
(A simple explanation about the view of memory from the graphics card vs. the system would be helpful. I found the following, but I could use more details:
NOTE:The fglrx 8.32.5 driver makes NO calls to the following registers (I have a 200M w/128M sideport and no UMA):
However, driver does set RADEON_CP_CSQ_CNTL to 0x80000000, which is not defined anywhere that I've found...
another quick hack
method might be to place the CP in the reserved framebuffer memory (as
it is all UMA) and see if that works....
In my BIOS, I've configured things so that I have no UMA memory and only 128MB of sideport. (If I turn on UMA, the 8.32.5 driver gets unstable...) Does this mean that I shouldn't be using the GART at all?
The card expects the ring buffer to be at 0x58000000.. (The FB begins at 0x50000000... I think that this is a bus address..)
How do I get that region mmaped into my virtual address space, so that the kernel can actually write commands to the proper location?