#17 systemverilog support for ctags

open
nobody
None
5
2014-06-24
2010-05-13
Vikram Khosa
No

Hi all,

I worked on a personal project last fall to develop a Systemverilog parser for ctags-5.8.

It supports most language features (based on the BNF from the IEEE 1800 spec draft). I\'ve been using it for actual development for the last few months and I can safely venture to call it beta quality.

I\'m not quite sure about the submission procedure and whether I need some sort of developer access to be able to checkin my changes? Could one of the existing developers perhaps point me the way?

As far as I can tell, no one else has been working on SV support -- I\'m willing to become a maintainer of this language support if warranted.
.
Thanks,
Vikram Khosa

Related

Support Requests: #17

Discussion

<< < 1 2 3 4 > >> (Page 2 of 4)
  • Steve
    Steve
    2012-11-20

    Sorry, word wrap messed that up pretty bad. There are three lines from the tags file shown. I'm trying again here, trying to prevent word wrap, and with a blank line between them (in case it wraps again.)

    RESPONSE_LOG2_DEPTH upa.sv /^ input logic clock,$/;" i undefined/global:upa

    logic upa.sv /^ output logic [UPDATE_FIFO_WIDTH-1:0] upa_update_fifo,$/;" C undefined/global:upa

    upa_final upa.sv /^);$/;" K undefined/global:upa

     
  • Vikram Khosa
    Vikram Khosa
    2012-12-02

    Johannes, I debugged your segfault -- the problem is that I was exiting the loop (early) on encountering a semicolon within a block scope. I think commenting out line 1112 : "loop = FALSE" inside the ";" case of processBlockAssocTag(...) in systemverilog.c should work as a simple fix for now (although the "clk" identifier will still not be tagged with the implicit "reg" or "logic" type). I will need to test this a bit more thoroughly and include it in a consolidated patch later.

     
  • Vikram Khosa
    Vikram Khosa
    2012-12-02

    Steve, thanks for testing it out. Yes, agree that tagging for typedefs & module parameters absolutely needs to be fixed. I will work on that and notify you once I have a patch ready.

    As for the useless block tags, I had included them for completeness sake. These can be easily filtered out by editing the following line in your taglist.vim (remove the mappings for the ones you don't care about).

    "systemverilog language
    let s:tlist_def_verilog_systemverilog_settings = 'verilog_systemverilog;a:access;b:always;c:assertion;' .
    \ 'd:case;e:clocking;f:chandle;g:checker;h:config;i:constant;' .
    \ 'j:constraint;l:covergroup;m:coverpoint;n:coverbin;o:class;' .
    \ 'p:enum;q:event;r:final;s:fork;t:function;u:generate;v:imexport;' .
    \ 'w:implementation;x:include;y:inheritance;z:initial;A:interface;' .
    \ 'B:int_atomic;C:int_vector;E:lifetime;F:linkage;G:module;H:net;' .
    \ 'I:non-integral;J:package;K:port;L:primitive;M:program;N:property;' .
    \ 'O:qualifier;P:randsequence;Q:seqblk;R:sequence;S:specify;T:string;' .
    \ 'U:strunion;V:table;W:task;X:timespec;Y:typedef;Z:void'

     
  • Hi Vikram,
    I tested your proposition by commenting out line 1112 and it solves the segfault with the clock generator.
    I wouldn't expect to tag the clk in this case which was defined some lines before. I guess, only implicit defined single bit wires are allowed and it would be no killer, if these don't get tagged.

    The problem is, that I now got further through our design database encountering another segmentation fault. This has to do with labeled fork-join blocks.

    Some other minor problems show up, when multiple signals are defined in the same statement.

    The following dummy module shows the problems I discoverd up to now:

    module test (read_data);

    input [7:0]read_data; // eats up first letter -> ead_data

    logic select, ready, busy; // only "busy" gets its entry in tag list

    wire signed [7:0] wave; // gets entered as "wire" not as "wave"
    // might be the same problem as already reported by steve

    // uncomment the label after fork and it will lead to a segfault
    initial
    begin
    fork//: labeled_block
    begin
    $display("Hello World!");
    end

    $display("Hello World!");

    begin
    $display("Hello World!");
    end
    join
    end

    always @(wave)
    a_no_undefined: assert (!$isunknown(wave) && // I would expect a tag here, but
    !$isunknown(busy)) // tag gets positioned to this line
    else
    $warning("Internal signal is undefined!");
    endmodule

    Anyways, it looks very promising and I hope you can fix the problems.
    I can test you patches on our design database, which seems to include enough different constructs to discover hidden problems.

    Johannes

     
  • justrajdeep
    justrajdeep
    2013-07-11

    Hi
    it will help a lot for young people like us who are just starting with both system verilog and vim to get ctags support.
    Really looking forward to this.

     
  • Suresh Mathew
    Suresh Mathew
    2013-12-03

    Hi Vikram, Was this code released into the main distribution?

     
  • Adam Krolnik
    Adam Krolnik
    2013-12-18

    Yes, would love to be able to get this together for 2014.

     
    • Suresh Mathew
      Suresh Mathew
      2013-12-18

      Hi adam, do you have a date for the release?
      On Dec 18, 2013 12:08 PM, "Adam Krolnik" adamkr@users.sf.net wrote:

      Yes, would love to be able to get this together for 2014.

      Status: open
      Created: Thu May 13, 2010 03:53 AM UTC by Vikram Khosa
      Last Updated: Tue Dec 03, 2013 02:19 PM UTC
      Owner: nobody

      Hi all,

      I worked on a personal project last fall to develop a Systemverilog parser
      for ctags-5.8.

      It supports most language features (based on the BNF from the IEEE 1800
      spec draft). I\'ve been using it for actual development for the last few
      months and I can safely venture to call it beta quality.

      I\'m not quite sure about the submission procedure and whether I need some
      sort of developer access to be able to checkin my changes? Could one of the
      existing developers perhaps point me the way?

      As far as I can tell, no one else has been working on SV support -- I\'m
      willing to become a maintainer of this language support if warranted.
      .
      Thanks,
      Vikram Khosa


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      Related

      Support Requests: #17

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  • Steve
    Steve
    2013-12-18

    Honestly, I found the support pretty weak, as noted in my prior comments. It really needs to be able to deal with tagging of user defined objects (like typedef struct) correctly, needs to lose all the non-sense tags for every begin and end, and properly treat them like the braces they are, etc. I have a version partially finished that is based on c.c that includes proper support for these things plus compiler directives, namespaces, etc. It certainly isn't ready for prime time yet, but I'd be more than happy to share the load if another developer or two wanted to help get it there.

     
    • Adam Krolnik
      Adam Krolnik
      2014-01-09

      Hi Steve;
      How about posting your current work for others to see ?

       
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