#79 Add support for Verilog 2001

open
nobody
None
5
2011-10-08
2011-10-08
Elias Wang
No

In the following case, ctags generates wrong tags
// Signed arithmetic extension
reg signed [63:0] data;
// Combined port and data type declarations
output reg [7:0] y;
// ANSI-style input and output declarations
module mux8 (
output reg [7:0] y,
input wire [7:0] a,
input wire [7:0] b,
input wire en );

Reference: http://www.sutherland-hdl.com/papers/2000-HDLCon-paper_Verilog-2000.pdf

Discussion

  • Elias Wang
    Elias Wang
    2011-10-08

    changes for supporting verilog 2001

     
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  • Elias Wang
    Elias Wang
    2011-10-08

    test case for this patch

     
    Attachments