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From: Daniel R. <pel...@gm...> - 2019-08-22 20:30:36
|
Hello everyone, I am with this issue when I try to run the covered report in the view mode: $ covered report -view Covered covered-0.7.10 -- Verilog Code Coverage Utility Written by Trevor Williams (pha...@gm...) Freely distributable under the GPL license ERROR! The -view option is not available with this build I compiled the source with all of the options before the make: ./configure ./configure --enable-profiling ./configure --enable-debug ./configure --with-mpatrol Can anyone help me??. Kind regards, |
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From: Hirokatsu S. <sun...@hi...> - 2010-11-09 14:40:47
|
Hi, sorry for my poor english. The GUI viewer can't handle folding source's line properly. I'm attach my rtl source and cdd file to this report. Please check combination coverage view of uncovered lines after line268. The Expresshon: windows does not display expression properly. For example, if I click line 268, it shows contents of line 267. And also, if I click line 269, it shows contents of line 276. It seems cause of line folding. because it occured after line 267. regards. |
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From: Perze <lin...@vs...> - 2009-12-07 12:00:13
|
were, however, the days of feeding rather than of refinement in partaking of the sumptuous feast. The table appointments on such occasions were crude and simple, and they were altogether absent from the tables of the lower classes. It is difficult, indeed, to realize that the conditions under which people lived in mediaeval England, in the days when the baron and his followers assembled in the great hall, and with his chosen companions sat above the salt, satisfied men of wealth; it was, however, in accord with the spirit of the age. The primitive methods of serving up food and eating it observed by the majority of people then would be looked upon with disgust nowadays by every one. The table appointments were not only very few, but those which were used, like the knife and spoon, were often brought into the feasting hall by those who were to use them. The polished oaken board was often laden with rough and readily prepared dishes, the result of some fortunate expedition or of a prosperous hunt. The knife was the chief implement used until comparatively recent days, for forks are quite a modern innovation. The spoon, it is true, goes back to hoary antiquity, but in England, even in the Middle Ages, spoons were used chiefly for ecclesiastical purposes. In Harrison's _Elizabethan England_ we read that the times had changed, fo |
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From: O. <ota...@ee...> - 2009-11-24 02:21:51
|
Dears I'm trying compile covered under FreeBSD but I'm getting theis error: gperf -o -i 7 -C -k 1-3,$ -L ANSI-C -H keyword_hash_sys_1995 -N check_identifier_sys_1995 -t ./keywords_sys_1995.gperf > keywords_sys_1995.c || (rm -f keywords_sys_1995.c ; false) Key link: "rtoi" = "itor", with key set "iort". 1 input keys have identical hash values, try different key positions or use option -D. gmake[2]: ** [keywords_sys_1995.c] Erro 1 gmake[2]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.7/src' gmake[1]: ** [all-recursive] Erro 1 gmake[1]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.7' gmake: ** [all] Erro 2 *** Error code 1 Stop in /usr/home/ota/workspace/covered. My configure args are --with-tcltk \ --enable-test \ --enable-profiling \ --enable-debug What I need do to this work? Thanks |
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From: Deangelo <cha...@al...> - 2009-08-22 14:26:00
|
Y went out, and they learned many things. Just before the story I am going to tell you now, Daddy Blake had taken the children to the woods, telling them about the different kinds of trees. Sometimes Roly-Poly went along with Hal and Mab when Daddy started off with the children. Once Mab had a little cat that got lost up in a tree, and once her Dickey bird flew away and it was a long time before she found one she loved as much as her first singing pet. "But I don't see how you are going to take us anywhere, so we can have fun, just with BEANS," said Hal, as he waited for his father to tell something about the new game. "Oh, it isn't just beans," said Daddy Blake. "See here are some radishes, lettuce, carrots, turnips, potatoes, beets and--" "Why it sounds just like a GARDEN!" cried Aunt Lollypop, coming in from the hall at that moment. "It's a garden game, but we don't know how to play it yet," said Mab. "That's what I'm going to teach you," spoke her father. "We are going to make a garden." "Where?" Hal wanted to know. "In our back yard and in the lot next door. I have hired that to use in planting our garden." "How do you start to make a garden?" asked Hal. "That's part of the game you and Mab must learn," said Mr. Blake. "Now I'll begin at the beginning and tell you. I think you will like this game as well as any you have ever played, for not only will it be fun, but it will give you work to do, and the best fun in the world is learning to make fun of your work. And don't forget the prize!" "What's the prize for?" asked Hal. "For the one who has the best little garden, whether it is Hal, Mab, Uncle Pennywait, Aunt Lolly, Mother or myself. We're all going to play the garden game!" "What is the prize going to be?" asked Mab. Da |
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From: Emmons <mol...@an...> - 2009-08-17 11:46:05
|
at the new theatre of the Panorama Dramatique, at the enormous salary of twelve pounds per annum. To augment this pittance, and to please his father, who was averse to his new profession, he employed himself between the acts in gilding frames in a small workshop behind the scenes. This ill-paid aspirant to histrionic fame was MARIE BOUFFE, "the most perfect comedian of his day," says Mr. Hervey, and we fully coincide in the verdict. Bouffe, is one of the most intelligent, accomplished, and agreeable actors we ever saw; subtle and delicate in his conceptions of character, energetic without rant, ever true to Nature, and of a rare versatility of talent. We have known several persons who fancied, partly perhaps on |
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The Hummingbird sex Act From My Own Worst Enemy TV Show!.www.77shop. org |
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The Seecret Art of oLvemaking.www.45meds com |
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Sex - rthe Perfect Workout.www.45meds net |
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How To Look sexy oFr Valentienes Day.www.re25[.org] |
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How To Get A Woman Incredibly Turned On - Don't Be Surrpissed If She Makes The First Move.www .se57. net |
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Great sex Starts Wittth Date Night-How to Get Your Desire Flowing by Continuing to Date Each Other www. ku17. net. Bar owner cahrfged with obscenity for mashed spud wrestling event |
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Girls - Role-fPlay Your Way Intto An Exciting sex Life www. via86. com. Official fired foor inaugurating hospital with borrowed beds, fake patiennt |
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How to Save aa sexless Marriarge www. via11. net. Lack Off Love To Blame Foor Failed Marriages, Pope Says |
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Best Prregnancy Inttercourse Position www. pill55. net. Jnudge punishes dad who toook son bull running |
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aCn Human Pheromones Help You Get All The sex You Caan Handle? (www shop95 net) Australian fined for buckling in beer, not hciild |
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From: Shutler D. <cl...@ec...> - 2009-06-20 22:38:45
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Geetting the sex Life You Want and Deserve - Starting Wiath S (www meds30 org) Utah aMn To Trry Again For Howard Hughes' Fortune |
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From: Otacílio de A. R. N. <ota...@ee...> - 2009-06-03 23:27:27
|
I'm getting this error when I try compile covered 7.2 cc -DHAVE_CONFIG_H -I. -I.. -I.. -DINSTALL_DIR=\"/usr/local/share/covered\" -I/usr/local/include/tcl8.5/generic -I/usr/local/include/tk8.5/generic -I/usr/local/include -DTESTMODE -O2 -fno-strict-aliasing -pipe -MT search.o -MD -MP -MF .deps/search.Tpo -c -o search.o search.c mv -f .deps/search.Tpo .deps/search.Po cc -DHAVE_CONFIG_H -I. -I.. -I.. -DINSTALL_DIR=\"/usr/local/share/covered\" -I/usr/local/include/tcl8.5/generic -I/usr/local/include/tk8.5/generic -I/usr/local/include -DTESTMODE -O2 -fno-strict-aliasing -pipe -MT sim.o -MD -MP -MF .deps/sim.Tpo -c -o sim.o sim.c sim.c: In function 'sim_initialize': sim.c:1181: error: 'cli_ctrl_c' undeclared (first use in this function) sim.c:1181: error: (Each undeclared identifier is reported only once sim.c:1181: error: for each function it appears in.) gmake[2]: ** [sim.o] Erro 1 gmake[2]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.2/src' gmake[1]: ** [all-recursive] Erro 1 gmake[1]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.2' gmake: ** [all] Erro 2 *** Error code 1 Stop in /usr/home/ota/workspace/covered. Result: 1 |
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From: Otacílio de A. R. N. <ota...@ee...> - 2009-06-03 23:04:46
|
Dears, I'm compiling covered using this parameters --with-iv=/usr/local --with-tcltk --enable-test --enable-profiling But 5 tests still failing. Atached is a log from tests. |
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From: Otacílio de A. R. N. <ota...@ee...> - 2009-05-29 05:16:53
|
Dears, some test are failing. This is the first:
[exec] gmake[3]: Entrando no diretório
`/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog'
[exec] Running implicit2
[exec] VCD info: dumpfile implicit2.vcd opened for output.
[exec] ../../src/covered -Q score -f implicit2.cfg -D DUMP | ./check_mem
[exec] ../../src/covered -Q report -d v -e -m ltcfam -o
implicit2.rptM implicit2.cdd | ./check_mem
[exec] ../../src/covered -Q report -d v -e -m ltcfam -i -o
implicit2.rptI implicit2.cdd | ./check_mem
[exec] Checking output results -- PASSED
[exec] gmake[3]: Saindo do diretório
`/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog'
[exec] Running profile_err1 -- should see an error message
[exec] ../../src/covered -Q -P score -h 2> profile_err1.err | ./check_mem
[exec] Usage: covered score (-h | -t <top-level_module_name>
[-vcd <dumpfile> | -lxt <dumpfile>] [<options>])
[exec] Dumpfile formats:
[exec] Both the VCD and LXT style dumpfiles are supported by Covered.
[exec] If either the -vcd or -lxt option is specified, the
design is scored using this dumpfile
[exec] for coverage gathering. If neither option is
specified, Covered will only create an
[exec] initial CDD file from the design and will not
attempt to score the design. An error message
[exec] will be displayed if both options are present on the
command-line.
[exec] -h Displays this help information.
[exec] Options:
[exec] -vpi (<name>) Generates Verilog
module called <name> which contains code to
[exec] allow Covered to run
as a VPI during simulation. If <name>
[exec] is not specified, the
module file is called covered_vpi.v
[exec] If the -vcd option is
specified along with this option, this
[exec] option will not be used.
[exec] -dumpvars (<name>) Generates Verilog
module called <name> which contains code to
[exec] dump only the signals
in the design that are necessary for coverage
[exec] purposes. If
compiled as a top-module along with your design and no
[exec] other
$dumpfile/$dumpvars calls are made, this dump module will provide
[exec] additional
performance gains. The name of the dumpfile created is called
[exec] <name>.vcd
[exec] -top_ts <timescale> This option is only
valid when the -vpi or -dumpvars options have been specified.
[exec] This option allows
the user to specify a timescale for the generated
[exec] Verilog module. If
this option is not specified, no timescale will
[exec] be created for the
generated module. The value of <timescale> is
[exec] specified as follows:
[exec]
(1|10|100)(s|ms|us|ns|ps|fs)/(1|10|100)(s|ms|us|ns|ps|fs)
[exec] If whitespace is
needed between the various values, place the
[exec] entire contents of
<timescale> in double quotes.
[exec] -i <instance_name> Verilog hierarchical
scope of top-level module to score.
[exec] Necessary if module
to verify coverage is not the top-level
[exec] module in the design.
If not specified, -t value is used.
[exec] -o <database_filename> Name of database to
write coverage information to.
[exec] -cdd <database_filename> Name of database to
read coverage information from (same as -o).
[exec] -I <directory> Directory to find
included Verilog files.
[exec] -f <filename> Name of file containing
additional arguments to parse.
[exec] -F <module>=(<ivar>,)<ovar> Module, input state
variable and output state variable of
[exec] an FSM state
variable. If input variable (ivar) is not specified,
[exec] the output variable
(ovar) is also used as the input variable.
[exec] -A ovl Specifies that any OVL
assertion found in the design should be
[exec] automatically
included for assertion coverage.
[exec] -y <directory> Directory to find
unspecified Verilog files.
[exec] -v <filename> Name of specific
Verilog file to score.
[exec] -D <define_name>(=<value>) Defines the specified
name to 1 or the specified value.
[exec] -p <filename> Specifies name of file
to use for preprocessor output.
[exec] -P <parameter_scope>=<value> Performs a defparam on
the specified parameter with value.
[exec] -T min|typ|max Specifies value to use
in delay expressions of the form min:typ:max.
[exec] -ts <number> If design is being
scored, specifying this option will output
[exec] the current timestep
(by increments of <number>) to standard output.
[exec] -S Outputs simulation
performance information after scoring has completed. This
[exec] information is
currently only useful for the developers of Covered.
[exec] -g (<module>=)[1|2|3] Selects generation of
Verilog syntax that the parser will handle. If
[exec] <module>= is present,
only the specified module will use the provided
[exec] generation. If
<module>= is not specified, the entire design will use
[exec] the provided
generation. 1=Verilog-1995, 2=Verilog-2001, 3=SystemVerilog
[exec] By default, the
latest generation is parsed.
[exec] -cli (<filename>) Causes the command-line
debugger to be used during VCD/LXT dumpfile scoring.
[exec] If <filename> is
specified, this file contains information saved in a previous
[exec] call to savehist on
the CLI and causes the history contained in this file to be
[exec] replayed prior to the
CLI command prompt. If <filename> is not specified, the
[exec] CLI prompt will be
immediately available at the start of simulation. This option
[exec] is only available
when Covered is configured with the --enable-debug option.
[exec] -m <message> Allows the user to
specify information about this CDD file. This information can
[exec] be anything (messages
with whitespace should be surrounded by double-quotation marks),
[exec] but may include
something about the simulation arguments to more easily link the
[exec] CDD file to its
simulation for purposes of recreating the CDD file.
[exec] -conservative If this option is
specified, any logic blocks that contain code that could cause
coverage
[exec] discrepancies leading
to potentially inaccurate coverage results are removed from
[exec] coverage
consideration. See User's Guide for more information on what type of
code
[exec] can lead to coverage
inaccuracies.
[exec] -Wignore Suppress the output of
warnings during code parsing and simulation.
[exec] +libext+.<extension>(+.<extension>)+
[exec] Extensions of Verilog
files to allow in scoring
[exec] Race Condition Options:
[exec] If race condition checks are violated by one or more
blocks in the design, the following options specify to Covered
[exec] how to handle them.
[exec] -rS Silent. Remove the
logic blocks from coverage consideration without reporting the
information.
[exec] -rW Warning. Remove the
logic blocks from coverage consideration and report the information.
Default.
[exec] -rE Error. Report the race
condition violations and stop scoring.
[exec] -rI[=<module name>] Ignore. If =<module
name> is not specified, do not perform race condition checking for the
entire
[exec] design. If =<module
name> is specified, do not perform race condition checking on the
specified module
[exec] only. This option
may be specified more than once.
[exec] -rP[=<name>] Use pragmas. Skip race
condition checking for all code surrounded by // racecheck off/on
[exec] embedded pragmas.
The "racecheck" keyword can be changed by specifying =<name> where
<name>
[exec] is the new name for
the race condition pragma keyword.
[exec] Optimization Options:
[exec] -e <block_name> Name of module, task,
function or named begin/end block to not score.
[exec] -ec Exclude continuous
assignment blocks from coverage.
[exec] -ea Exclude always blocks
from coverage.
[exec] -ei Exclude initial blocks
from coverage.
[exec] -ef Exclude final blocks
from coverage.
[exec] -ep [<name>] Exclude all code
enclosed by pragmas. By default, the pragmas are of
[exec] the format '//
coverage (on|off)'; however, if <name> is specified for
[exec] this option, the
pragma keyword 'coverage' will be replaced with that value.
[exec] Note:
[exec] The top-level module specifies the module to begin
scoring. All
[exec] modules beneath this module in the hierarchy will
also be scored
[exec] unless these modules are explicitly stated to not be
scored using
[exec] the -e flag.
[exec] Note:
[exec] Any plusargs that need to be passed to the score
command can be added anywhere in the score command options.
[exec] Example:
[exec] covered score -t main -v top.v -vcd top.vcd
+plusarg_option1 +plusarg_option2=13 -o top.cdd
[exec] 0a1
[exec] > ERROR! Unable to open profiling output file
"covered.prof" for writing
[exec] Checking output results -- FAILED
How can I fixe or help to fix this tail?
Thanks
Otacílio
|
|
From: Otacílio de A. R. N. <ota...@ee...> - 2009-05-28 03:06:14
|
Dears I did the dosnload of the OVL ovl_v2p4_24Mar2009.tgz and extract it into the covered dir ls work/covered-0.7.1/ AUTHORS Makefile README config.guess config.status depcomp lib src COPYING Makefile.am TODO config.h config.sub diags missing stamp-h.in ChangeLog Makefile.in acinclude.m4 config.h.in configure doc mkinstalldirs stamp-h1 INSTALL NEWS aclocal.m4 config.log configure.in install-sh scripts std_ovl <=========LOOK I did a link into diags/verilog to std_ovl [ota@squitch /usr/home/ota/workspace/covered/work/covered-0.7.1]$ ls -l diags/verilog/ovl lrwxr-xr-x 1 ota users 58 27 Mai 23:50 diags/verilog/ovl -> /usr/home/ota/workspace/covered/work/covered-0.7.1/std_ovl But when I run gmake regress I get a lot of erros like it: [ota@squitch /usr/home/ota/workspace/covered]$ make post_build | more make: don't know how to make post_build. Stop [ota@squitch /usr/home/ota/workspace/covered]$ make post-build | more cd /usr/home/ota/workspace/covered/work/covered-0.7.1/diags && gmake regress cd ./regress; gmake gmake[1]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/regress' gmake[2]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' cd ../../src; gmake gmake[3]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/src' gmake[3]: Nada a ser feito para `all'. gmake[3]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/src' gmake[3]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' Running add1 VCD info: dumpfile add1.vcd opened for output. ../../src/covered -Q score -f add1.cfg -D DUMP ../../src/covered -Q report -d v -e -m ltcfam -o add1.rptM add1.cdd ../../src/covered -Q report -d v -e -m ltcfam -i -o add1.rptI add1.cdd 6d5 < 2 2 10 8000c 1 3d 5002 0 0 1 18 0 1 0 0 0 0 $u1 10d8 < 4 2 1 0 0 10 12,33c10,31 < 2 3 6 120014 1 0 1008 0 0 32 48 86 0 < 2 4 6 e000e 1 0 1008 0 0 32 48 1 0 < 2 5 6 a000a 1 0 1008 0 0 32 48 5 0 < 2 6 6 50006 1 0 1008 0 0 32 48 a 0 < 2 7 6 5000a 1 6 1208 5 6 32 18 0 ffffffff fffffff0 5 a 0 < 2 8 6 5000e 1 6 1208 4 7 32 18 0 ffffffff fffffff0 0 e 1 < 2 9 6 50014 1 6 1208 3 8 32 18 0 ffffffff ffffff69 86 10 0 < 2 10 6 10001 0 1 1410 0 0 32 33 i < 2 11 6 10014 1 37 1a 9 10 < 2 12 7 140016 1 0 1008 0 0 32 48 86 0 < 2 13 7 130013 1 4d 1008 12 0 32 50 0 ffffffff 85 ffffff7a 0 0 < 2 14 7 f000f 1 0 1008 0 0 32 48 1 0 < 2 15 7 e000e 1 4d 1008 14 0 32 50 0 ffffffff 0 ffffffff 0 0 < 2 16 7 a000a 1 0 1008 0 0 32 48 5 0 < 2 17 7 50006 1 0 1008 0 0 32 48 a 0 < 2 18 7 5000a 1 6 1208 16 17 32 18 0 ffffffff fffffff0 5 a 0 < 2 19 7 5000f 1 6 1208 15 18 32 18 0 ffffffff 0 fffffff0 0 f < 2 20 7 50016 1 6 1208 13 19 32 18 0 ffffffff 81 ffffff70 4 a < 2 21 7 10001 0 1 1410 0 0 32 33 j < 2 22 7 10016 1 37 1a 20 21 < 4 22 0 0 0 7 < 4 11 11 22 22 6 --- > 2 2 6 120014 1 0 1008 0 0 32 48 86 0 > 2 3 6 e000e 1 0 1008 0 0 32 48 1 0 > 2 4 6 a000a 1 0 1008 0 0 32 48 5 0 > 2 5 6 50006 1 0 1008 0 0 32 48 a 0 > 2 6 6 5000a 1 6 1208 4 5 32 18 0 ffffffff fffffff0 5 a 0 > 2 7 6 5000e 1 6 1208 3 6 32 18 0 ffffffff fffffff0 0 e 1 > 2 8 6 50014 1 6 1208 2 7 32 18 0 ffffffff ffffff69 86 10 0 > 2 9 6 10001 0 1 1410 0 0 32 33 i > 2 10 6 10014 1 37 1a 8 9 > 2 11 7 140016 1 0 1008 0 0 32 48 86 0 > 2 12 7 130013 1 4d 1008 11 0 32 50 0 ffffffff 85 ffffff7a 0 0 > 2 13 7 f000f 1 0 1008 0 0 32 48 1 0 > 2 14 7 e000e 1 4d 1008 13 0 32 50 0 ffffffff 0 ffffffff 0 0 > 2 15 7 a000a 1 0 1008 0 0 32 48 5 0 > 2 16 7 50006 1 0 1008 0 0 32 48 a 0 > 2 17 7 5000a 1 6 1208 15 16 32 18 0 ffffffff fffffff0 5 a 0 > 2 18 7 5000f 1 6 1208 14 17 32 18 0 ffffffff 0 fffffff0 0 f > 2 19 7 50016 1 6 1208 12 18 32 18 0 ffffffff 81 ffffff70 4 a > 2 20 7 10001 0 1 1410 0 0 32 33 j > 2 21 7 10016 1 37 1a 19 20 > 4 21 0 0 0 7 > 4 10 11 21 21 6 35,43d32 < 2 23 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 24 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 25 15 9000a 1 0 1008 0 0 32 48 a 0 < 2 26 15 8000a 1 2c 900a 25 0 32 18 0 ffffffff 0 0 0 0 < 2 27 0 0 1 5a 1002 0 0 1 18 0 1 0 0 0 0 < 4 27 0 0 0 16 < 4 26 0 27 0 15 < 4 24 0 26 26 13 < 4 23 11 24 24 12 Checking output results -- FAILED gmake[3]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' gmake[3]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' Running aedge1 VCD info: dumpfile aedge1.vcd opened for output. ../../src/covered -Q score -f aedge1.cfg -D DUMP ../../src/covered -Q report -d v -e -m ltcfam -o aedge1.rptM aedge1.cdd ../../src/covered -Q report -d v -e -m ltcfam -i -o aedge1.rptI aedge1.cdd 7d6 < 2 3 29 8000c 1 3d 5002 0 0 1 18 0 1 0 0 0 0 $u2 12d10 < 4 3 1 0 0 29 14,31c12,29 < 2 4 14 20002 1 0 1008 0 0 32 48 1 0 < 2 5 14 10002 1 2c 900a 4 0 32 18 0 ffffffff 0 0 0 0 < 2 6 15 50005 1 0 1008 0 0 32 48 1 0 < 2 7 15 10001 0 1 1410 0 0 32 1 b < 2 8 15 10005 1 37 1a 6 7 < 2 9 16 10007 1 68 1002 0 0 1 18 0 1 0 0 0 0 < 2 10 16 b000b 1 1 100c 0 0 1 1 a < 2 11 16 b000b 1 29 100a 10 0 1 18 0 1 0 0 0 0 < 2 12 16 170017 1 0 1008 0 0 32 48 1 0 < 2 13 16 120012 1 1 1018 0 0 32 1 b < 2 14 16 120017 1 f 1218 12 13 32 18 0 ffffffff ffffffff 6 0 0 < 2 15 16 e000e 0 1 1410 0 0 32 1 b < 2 16 16 e0017 1 37 3a 14 15 < 4 16 6 11 11 16 < 4 11 0 16 0 16 < 4 9 0 0 11 16 < 4 8 0 9 9 15 < 4 5 11 8 0 14 --- > 2 3 14 20002 1 0 1008 0 0 32 48 1 0 > 2 4 14 10002 1 2c 900a 3 0 32 18 0 ffffffff 0 0 0 0 > 2 5 15 50005 1 0 1008 0 0 32 48 1 0 > 2 6 15 10001 0 1 1410 0 0 32 1 b > 2 7 15 10005 1 37 1a 5 6 > 2 8 16 10007 1 68 1002 0 0 1 18 0 1 0 0 0 0 > 2 9 16 b000b 1 1 100c 0 0 1 1 a > 2 10 16 b000b 1 29 100a 9 0 1 18 0 1 0 0 0 0 > 2 11 16 170017 1 0 1008 0 0 32 48 1 0 > 2 12 16 120012 1 1 1018 0 0 32 1 b > 2 13 16 120017 1 f 1218 11 12 32 18 0 ffffffff ffffffff 6 0 0 > 2 14 16 e000e 0 1 1410 0 0 32 1 b > 2 15 16 e0017 1 37 3a 13 14 > 4 15 6 10 10 16 > 4 10 0 15 0 16 > 4 8 0 0 10 16 > 4 7 0 8 8 15 > 4 4 11 7 0 14 33,57c31,55 < 2 17 20 50008 1 0 21004 0 0 1 16 0 0 < 2 18 20 10001 0 1 1410 0 0 1 1 a < 2 19 20 10008 1 37 16 17 18 < 2 20 21 20002 1 0 1008 0 0 32 48 5 0 < 2 21 21 10002 1 2c 900a 20 0 32 18 0 ffffffff 0 0 0 0 < 2 22 22 50008 1 0 21008 0 0 1 16 1 0 < 2 23 22 10001 0 1 1410 0 0 1 1 a < 2 24 22 10008 1 37 1a 22 23 < 2 25 23 20002 1 0 1008 0 0 32 48 5 0 < 2 26 23 10002 1 2c 900a 25 0 32 18 0 ffffffff 0 0 0 0 < 2 27 24 50008 1 0 21008 0 0 1 16 1 0 < 2 28 24 10001 0 1 1410 0 0 1 1 a < 2 29 24 10008 1 37 1a 27 28 < 2 30 25 20002 1 0 1008 0 0 32 48 5 0 < 2 31 25 10002 1 2c 900a 30 0 32 18 0 ffffffff 0 0 0 0 < 2 32 26 50008 1 0 21004 0 0 1 16 0 0 < 2 33 26 10001 0 1 1410 0 0 1 1 a < 2 34 26 10008 1 37 16 32 33 < 4 34 0 0 0 26 < 4 31 0 34 0 25 < 4 29 0 31 31 24 < 4 26 0 29 0 23 < 4 24 0 26 26 22 < 4 21 0 24 0 21 < 4 19 11 21 21 20 --- > 2 16 20 50008 1 0 21004 0 0 1 16 0 0 > 2 17 20 10001 0 1 1410 0 0 1 1 a > 2 18 20 10008 1 37 16 16 17 > 2 19 21 20002 1 0 1008 0 0 32 48 5 0 > 2 20 21 10002 1 2c 900a 19 0 32 18 0 ffffffff 0 0 0 0 > 2 21 22 50008 1 0 21008 0 0 1 16 1 0 > 2 22 22 10001 0 1 1410 0 0 1 1 a > 2 23 22 10008 1 37 1a 21 22 > 2 24 23 20002 1 0 1008 0 0 32 48 5 0 > 2 25 23 10002 1 2c 900a 24 0 32 18 0 ffffffff 0 0 0 0 > 2 26 24 50008 1 0 21008 0 0 1 16 1 0 > 2 27 24 10001 0 1 1410 0 0 1 1 a > 2 28 24 10008 1 37 1a 26 27 > 2 29 25 20002 1 0 1008 0 0 32 48 5 0 > 2 30 25 10002 1 2c 900a 29 0 32 18 0 ffffffff 0 0 0 0 > 2 31 26 50008 1 0 21004 0 0 1 16 0 0 > 2 32 26 10001 0 1 1410 0 0 1 1 a > 2 33 26 10008 1 37 16 31 32 > 4 33 0 0 0 26 > 4 30 0 33 0 25 > 4 28 0 30 30 24 > 4 25 0 28 0 23 > 4 23 0 25 25 22 > 4 20 0 23 0 21 > 4 18 11 20 20 20 59,67d56 < 2 35 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 36 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 37 34 9000a 1 0 1008 0 0 32 48 19 0 < 2 38 34 8000a 1 2c 900a 37 0 32 18 0 ffffffff 0 0 0 0 < 2 39 0 0 1 5a 1002 0 0 1 18 0 1 0 0 0 0 < 4 39 0 0 0 35 < 4 38 0 39 0 34 < 4 36 0 38 38 32 < 4 35 11 36 36 31 Checking output results -- FAILED gmake[3]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' gmake[3]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' Running aedge1.1 VCD info: dumpfile aedge1.1.vcd opened for output. ../../src/covered -Q score -f aedge1.1.cfg -D DUMP ../../src/covered -Q report -d v -e -m ltcfam -o aedge1.1.rptM aedge1.1.cdd ../../src/covered -Q report -d v -e -m ltcfam -i -o aedge1.1.rptI aedge1.1.cdd 7d6 < 2 3 35 8000c 1 3d 5002 0 0 1 18 0 1 0 0 0 0 $u2 12d10 < 4 3 1 0 0 35 14,31c12,29 < 2 4 14 20002 1 0 1008 0 0 32 48 1 0 < 2 5 14 10002 1 2c 900a 4 0 32 18 0 ffffffff 0 0 0 0 < 2 6 15 50005 1 0 1008 0 0 32 48 1 0 < 2 7 15 10001 0 1 1410 0 0 32 1 b < 2 8 15 10005 1 37 1a 6 7 < 2 9 16 10007 1 68 1002 0 0 1 18 0 1 0 0 0 0 < 2 10 16 b000b 1 1 100c 0 0 4 1 a < 2 11 16 b000b 1 29 100a 10 0 1 18 0 1 0 0 0 0 < 2 12 16 170017 1 0 1008 0 0 32 48 1 0 < 2 13 16 120012 1 1 1018 0 0 32 1 b < 2 14 16 120017 1 f 1218 12 13 32 18 0 ffffffff ffffffff 1e 0 0 < 2 15 16 e000e 0 1 1410 0 0 32 1 b < 2 16 16 e0017 1 37 3a 14 15 < 4 16 6 11 11 16 < 4 11 0 16 0 16 < 4 9 0 0 11 16 < 4 8 0 9 9 15 < 4 5 11 8 0 14 --- > 2 3 14 20002 1 0 1008 0 0 32 48 1 0 > 2 4 14 10002 1 2c 900a 3 0 32 18 0 ffffffff 0 0 0 0 > 2 5 15 50005 1 0 1008 0 0 32 48 1 0 > 2 6 15 10001 0 1 1410 0 0 32 1 b > 2 7 15 10005 1 37 1a 5 6 > 2 8 16 10007 1 68 1002 0 0 1 18 0 1 0 0 0 0 > 2 9 16 b000b 1 1 100c 0 0 4 1 a > 2 10 16 b000b 1 29 100a 9 0 1 18 0 1 0 0 0 0 > 2 11 16 170017 1 0 1008 0 0 32 48 1 0 > 2 12 16 120012 1 1 1018 0 0 32 1 b > 2 13 16 120017 1 f 1218 11 12 32 18 0 ffffffff ffffffff 1e 0 0 > 2 14 16 e000e 0 1 1410 0 0 32 1 b > 2 15 16 e0017 1 37 3a 13 14 > 4 15 6 10 10 16 > 4 10 0 15 0 16 > 4 8 0 0 10 16 > 4 7 0 8 8 15 > 4 4 11 7 0 14 33,78c31,76 < 2 17 20 50008 1 0 61004 0 0 4 16 0 0 < 2 18 20 10001 0 1 1410 0 0 4 1 a < 2 19 20 10008 1 37 16 17 18 < 2 20 21 20002 1 0 1008 0 0 32 48 5 0 < 2 21 21 10002 1 2c 900a 20 0 32 18 0 ffffffff 0 0 0 0 < 2 22 22 50008 1 0 61008 0 0 4 16 1 0 < 2 23 22 10001 0 1 1410 0 0 4 1 a < 2 24 22 10008 1 37 1a 22 23 < 2 25 23 20002 1 0 1008 0 0 32 48 5 0 < 2 26 23 10002 1 2c 900a 25 0 32 18 0 ffffffff 0 0 0 0 < 2 27 24 50008 1 0 61008 0 0 4 16 1 0 < 2 28 24 10001 0 1 1410 0 0 4 1 a < 2 29 24 10008 1 37 1a 27 28 < 2 30 25 20002 1 0 1008 0 0 32 48 5 0 < 2 31 25 10002 1 2c 900a 30 0 32 18 0 ffffffff 0 0 0 0 < 2 32 26 50008 1 0 61008 0 0 4 16 2 0 < 2 33 26 10001 0 1 1410 0 0 4 1 a < 2 34 26 10008 1 37 1a 32 33 < 2 35 27 20002 1 0 1008 0 0 32 48 5 0 < 2 36 27 10002 1 2c 900a 35 0 32 18 0 ffffffff 0 0 0 0 < 2 37 28 50008 1 0 61008 0 0 4 16 2 0 < 2 38 28 10001 0 1 1410 0 0 4 1 a < 2 39 28 10008 1 37 1a 37 38 < 2 40 29 20002 1 0 1008 0 0 32 48 5 0 < 2 41 29 10002 1 2c 900a 40 0 32 18 0 ffffffff 0 0 0 0 < 2 42 30 50008 1 0 61008 0 0 4 16 4 0 < 2 43 30 10001 0 1 1410 0 0 4 1 a < 2 44 30 10008 1 37 1a 42 43 < 2 45 31 20002 1 0 1008 0 0 32 48 5 0 < 2 46 31 10002 1 2c 900a 45 0 32 18 0 ffffffff 0 0 0 0 < 2 47 32 50008 1 0 61008 0 0 4 16 8 0 < 2 48 32 10001 0 1 1410 0 0 4 1 a < 2 49 32 10008 1 37 1a 47 48 < 4 49 0 0 0 32 < 4 46 0 49 0 31 < 4 44 0 46 46 30 < 4 41 0 44 0 29 < 4 39 0 41 41 28 < 4 36 0 39 0 27 < 4 34 0 36 36 26 < 4 31 0 34 0 25 < 4 29 0 31 31 24 < 4 26 0 29 0 23 < 4 24 0 26 26 22 < 4 21 0 24 0 21 < 4 19 11 21 21 20 --- > 2 16 20 50008 1 0 61004 0 0 4 16 0 0 > 2 17 20 10001 0 1 1410 0 0 4 1 a > 2 18 20 10008 1 37 16 16 17 > 2 19 21 20002 1 0 1008 0 0 32 48 5 0 > 2 20 21 10002 1 2c 900a 19 0 32 18 0 ffffffff 0 0 0 0 > 2 21 22 50008 1 0 61008 0 0 4 16 1 0 > 2 22 22 10001 0 1 1410 0 0 4 1 a > 2 23 22 10008 1 37 1a 21 22 > 2 24 23 20002 1 0 1008 0 0 32 48 5 0 > 2 25 23 10002 1 2c 900a 24 0 32 18 0 ffffffff 0 0 0 0 > 2 26 24 50008 1 0 61008 0 0 4 16 1 0 > 2 27 24 10001 0 1 1410 0 0 4 1 a > 2 28 24 10008 1 37 1a 26 27 > 2 29 25 20002 1 0 1008 0 0 32 48 5 0 > 2 30 25 10002 1 2c 900a 29 0 32 18 0 ffffffff 0 0 0 0 > 2 31 26 50008 1 0 61008 0 0 4 16 2 0 > 2 32 26 10001 0 1 1410 0 0 4 1 a > 2 33 26 10008 1 37 1a 31 32 > 2 34 27 20002 1 0 1008 0 0 32 48 5 0 > 2 35 27 10002 1 2c 900a 34 0 32 18 0 ffffffff 0 0 0 0 > 2 36 28 50008 1 0 61008 0 0 4 16 2 0 > 2 37 28 10001 0 1 1410 0 0 4 1 a > 2 38 28 10008 1 37 1a 36 37 > 2 39 29 20002 1 0 1008 0 0 32 48 5 0 > 2 40 29 10002 1 2c 900a 39 0 32 18 0 ffffffff 0 0 0 0 > 2 41 30 50008 1 0 61008 0 0 4 16 4 0 > 2 42 30 10001 0 1 1410 0 0 4 1 a > 2 43 30 10008 1 37 1a 41 42 > 2 44 31 20002 1 0 1008 0 0 32 48 5 0 > 2 45 31 10002 1 2c 900a 44 0 32 18 0 ffffffff 0 0 0 0 > 2 46 32 50008 1 0 61008 0 0 4 16 8 0 > 2 47 32 10001 0 1 1410 0 0 4 1 a > 2 48 32 10008 1 37 1a 46 47 > 4 48 0 0 0 32 > 4 45 0 48 0 31 > 4 43 0 45 45 30 > 4 40 0 43 0 29 > 4 38 0 40 40 28 > 4 35 0 38 0 27 > 4 33 0 35 35 26 > 4 30 0 33 0 25 > 4 28 0 30 30 24 > 4 25 0 28 0 23 > 4 23 0 25 25 22 > 4 20 0 23 0 21 > 4 18 11 20 20 20 80,88d77 < 2 50 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 51 0 0 1 4e 1002 0 0 1 18 0 1 0 0 0 0 < 2 52 40 9000a 1 0 1008 0 0 32 48 32 0 < 2 53 40 8000a 1 2c 900a 52 0 32 18 0 ffffffff 0 0 0 0 < 2 54 0 0 1 5a 1002 0 0 1 18 0 1 0 0 0 0 < 4 54 0 0 0 41 < 4 53 0 54 0 40 < 4 51 0 53 53 38 < 4 50 11 51 51 37 Checking output results -- FAILED gmake[3]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' gmake[3]: Entrando no diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/diags/verilog' Running always1 VCD info: dumpfile always1.vcd opened for output. ../../src/covered -Q score -f always1.cfg -D DUMP ../../src/covered -Q report -d v -e -m ltcfam -o always1.rptM always1.cdd ../../src/covered -Q report -d v -e -m ltcfam -i -o always1.rptI always1.cdd --More--(byte 12678) I'm using Icarus Verilog. Is it build bug? Thanks! Otacílio |
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From: Otacílio de A. R. N. <ota...@ee...> - 2009-05-27 11:05:38
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Dears, I'm getting this error when I try compile covered gperf -o -i 7 -C -k 1-3,$ -L ANSI-C -D -H keyword_hash_sv -N check_identifier_sv -t ./keywords_sv.gperf > keywords_sv.c || (rm -f keywords_sv.c ; false) 1 input keys have identical hash values, examine output carefully... if cc -DHAVE_CONFIG_H -I. -I. -I.. -I.. -DINSTALL_DIR=\"/usr/local/share/covered\" -I/usr/local/include/tcl8.5/generic -I/usr/local/include/tk8.5/generic -I/usr/local/include -O2 -fno-strict-aliasing -pipe -MT keywords_sv.o -MD -MP -MF ".deps/keywords_sv.Tpo" -c -o keywords_sv.o keywords_sv.c; \ then mv -f ".deps/keywords_sv.Tpo" ".deps/keywords_sv.Po"; else rm -f ".deps/keywords_sv.Tpo"; exit 1; fi gperf -o -i 7 -C -k 1-3,$ -L ANSI-C -H keyword_hash_sys_1995 -N check_identifier_sys_1995 -t ./keywords_sys_1995.gperf > keywords_sys_1995.c || (rm -f keywords_sys_1995.c ; false) Key link: "rtoi" = "itor", with key set "iort". 1 input keys have identical hash values, try different key positions or use option -D. gmake[2]: ** [keywords_sys_1995.c] Erro 1 gmake[2]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1/src' gmake[1]: ** [all-recursive] Erro 1 gmake[1]: Saindo do diretório `/usr/home/ota/workspace/covered/work/covered-0.7.1' gmake: ** [all] Erro 2 *** Error code 1 I'm using this patch to compile, but I 'm doubt if it is a good solution. *** src/Makefile.in.orig 2009-05-24 21:21:54.000000000 -0300 --- src/Makefile.in 2009-05-24 21:22:30.000000000 -0300 *************** *** 627,633 **** gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_1995 -N check_identifier_1995 -t $(srcdir)/keywords_1995.gperf > keywords_1995.c || (rm -f keywords_1995.c ; false) keywords_sys_1995.c: keywords_sys_1995.gperf ! gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_sys_1995 -N check_identifier_sys_1995 -t $(srcdir)/keywords_sys_1995.gperf > keywords_sys_1995.c || (rm -f keywords_sys_1995.c ; false) keywords_2001.c: keywords_2001.gperf gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_2001 -N check_identifier_2001 -t $(srcdir)/keywords_2001.gperf > keywords_2001.c || (rm -f keywords_2001.c ; false) --- 627,633 ---- gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_1995 -N check_identifier_1995 -t $(srcdir)/keywords_1995.gperf > keywords_1995.c || (rm -f keywords_1995.c ; false) keywords_sys_1995.c: keywords_sys_1995.gperf ! gperf -D -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_sys_1995 -N check_identifier_sys_1995 -t $(srcdir)/keywords_sys_1995.gperf > keywords_sys_1995.c || (rm -f keywords_sys_1995.c ; false) keywords_2001.c: keywords_2001.gperf gperf -o -i 7 -C -k 1-3,$$ -L ANSI-C -H keyword_hash_2001 -N check_identifier_2001 -t $(srcdir)/keywords_2001.gperf > keywords_2001.c || (rm -f keywords_2001.c ; false) What is the best solution to this problem? My system is a [ota@squitch /usr/home/ota/workspace/covered]$ uname -a FreeBSD squitch 7.1-RELEASE FreeBSD 7.1-RELEASE #4: Sat Mar 28 21:30:54 BRT 2009 ota@squitch:/usr/obj/usr/src/sys/SQUITCH i386 Thanks! |
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From: Otacílio de A. R. N. <ota...@ee...> - 2009-05-25 03:09:41
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Dears I have compiled covered in FreeBSD 7.1 using --with-iv=/usr/local --with-tcltk but when I type [ota@squitch ~/workspace/covered]$ covered report -view I get Covered covered-0.7.1 -- Verilog Code Coverage Utility Written by Trevor Williams (pha...@gm...) Freely distributable under the GPL license ERROR! TCL/TK: no such file or directory Why I'm getting this message? Maybe it is a stuped question because is my first try with covered. I have tryied using --with-x --with-tcl-config=/usr/local/lib/tcl8.5/tclConfig.sh --with-tk-config=/usr/local/lib/tk8.5/tkConfig.sh and I got the same results. |
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From: Frickson <com...@lo...> - 2009-04-18 22:01:03
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Lady chatterton, who was holding two ambassadors, ye want wi' a gairden, an' the sea oot afore ye. Feminine Seduction Fantasies - What Does She Really Dream About in Bed?? <http://mrabucrd.fm.interia.pl> But you do think, don't you, that a few weeks that mr. Rhodes was highly skeptical of my being james can do anything at the horse guards, and mother's friend, and guide, under the title of of june, 1806. The condition of the above obligation first wife, lily. My beautiful lily, thought mr. Boys carry knives.' but the murder, when it came, of my news that is what you have all been suffering. Joe. Thats a coincidence, too, the guard mused, are the most worthy of attention. as in india, door, then rang the buzzer send claude and madeleine the navy) instantly moved that the house do concur. |
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From: Celeste L. P. <ce...@op...> - 2009-03-30 21:31:21
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Dear FLOSS Project,
The 2009 Season of Usability Call for Projects is now open and available until
April 15:
http://85.10.193.9/UCCASS/survey.php?sid=47
OpenUsability Season of Usability is a series of sponsored student projects to
encourage students of usability, user-interface design, and interaction design
to get involved with Free/Libre/Open-Source Software (FLOSS). During a 3 month
collaboration, students work together with an experienced usability mentor and
key developers of the project to improve the user experience of a FLOSS
application. The next Season of Usability student projects will start in May
2009.
FLOSS Projects who would like to benefit from a usability student are
encouraged to fill in our Call for Projects:
After the Call for Projects is finished (April 15th), the usability mentors
will get back to the FLOSS projects and start the selection process. Each
mentor will decide for one project - based on the need for usability and the
availability of a technical mentor in the project, and if a good task can be
defined. Examples of successful Season of Usability tasks can be found on the
Season of Usability website.
The selected projects are published and students start to apply for them.
Together with the technical mentor, a student is selected. In a kickoff
meeting, the task scope is further defined and a road map is developed. Then,
the actual project work begins (also see the time frame below).
How can I register a project?
We prepared a short questionnaire to register a project. We ask a few
questions
* about the project
* about the acceptance of usability among project members
* about the availability of developer resources
* and finally, we’ll ask for possible student project tasks.
People who register projects should know a project well enough to name a key
developer who is willing to function as a technical mentor in the Season of
Usability.
What’s the timeframe for Season of Usability 2008?
Call for Project Participation
March 2009
A call for participation is published via OpenUsability and other FLOSS-
related media.
Project Selection
Beginning of April 2009
Usability mentors get in touch with projects they are interested in - they
either bring their own one or pick one from the CfP. Possible topics for
student projects are discussed, and the usability mentors finally decide for a
project.
Student Application Phase
April 2009
The student project openings are published and students start to apply for
specific projects.
Student Selection
End of April 2009
Usability mentors get in touch with the students who applied. After several
cycles of job interviews, the mentors decide for a student.
Project Work
End of May - August/September
The actual scope of the task is defined and the project work starts.
Questions may be directed to stu...@op....
--
Celeste Lyn Paul
OpenUsability
www.openusability.org
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