Behaviour of OR Gate?

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peter_d
2012-05-01
2013-04-29
  • peter_d
    peter_d
    2012-05-01

    I have a two input OR gate.  I have found that when the inputs switch over I am seeing a pulse on the output.

    i.e.
    CASE 1:
    Input 1 = 1
    Input 2 = 0
    Output = 1

    CASE 2:
    Input 1 = 0
    Input 2 = 1
    Output = 1

    So when the inputs change on the same clock pulse from CASE 1 to CASE 2 despite the output remaining at 1 there seems to be a on/off pulse.  I cannot see this visually but I can pick it up with a counter.

    Is this correct behaviour?  Is this how a gate would act in the real world or is this just how Logisim behaves?

    I am using an OR as the last stage before an output on a timer circuit that provides a maintained output for a fixed time.  However as described above, although the timer output appears to be constant there is actually a pulse.  Is there a simple way to buffer this to get round this effect?

    Thanks in advance for any comments or suggestions!

     
  • Marc Dendooven
    Marc Dendooven
    2012-05-01

    I suppose you use an invertor on one of the input's of the or. Don't forget this invertor has a delay.

     
  • Marc Dendooven
    Marc Dendooven
    2012-05-01

    see the difference between the following two designs: the first has a pulse since there is a delay in the invertor. this is what is called a race condition.
    the second design has not (in logisim). in the real world there could be a delay between the buffer and the inverter which could cause a pulse anyway. this is a typical problem in asynchrone design. to prevent this, synchrone designs are prefered.


    gtz