Hi, I have been looking around but haven’t seen decent support for SystemVerilog anywhere. I know there is Verilog support already but it doesn’t get me very far with being able to use CEDET’s feature set. So, I’m starting to think about doing it, myself. I already have some hacked in support using a regex language definition for CTAGS but that obviously has its limitations. Before I actually start with this project, I was wondering if anyone else already was working on something to this effect, and if so, if it is already available somewhere.
Also, I was wondering if my work for adding support should exist in any particular repository or if I can do this in my own repo (probably to be published to github) and that it can be merged back to CEDET’s repo later on, when it reaches a stable point?
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