#21 Test registers (and MSRs)

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nobody
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2012-10-15
2001-05-16
Matus Horvath
No

I would be really happy if bochs would support test
registers on a 486 and perhaps also MSRs that deal with
TLB access (I need to acces/update TLB directly for my
school project). Do you know about some other ix86
emulator that has this implemented? Would it be
possible to implement it in bochs?

Matus Horvath, horvathm@decef.elf.stuba.sk

Discussion

  • Bryce Denney
    Bryce Denney
    2001-05-17

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    A dangerous question... Anything can be implemented in
    bochs, given good enough documentation, some time, and sheer
    willpower!

    I am not really familiar with this part of the code, or
    indeed this part of the Intel processors. Could you specify
    which registers and MSRs are of use to you? Are you looking
    for the performance monitoring counters, or something that
    actually affects how the TLB behaves? If bochs already has
    the right behavior and we just need to add counters, that's
    pretty easy. If you could, please give pointers to the
    pages in the intel docs that describe what you are looking
    for. (I have IA32 software developers guide, 3 volumes.)

    If we do not have time to get these features added before
    your project is due, we won't complain if you add them and
    send in patches. ;-)

     
  • Matus Horvath
    Matus Horvath
    2001-05-17

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    486 (and 386) has special test registers TR6 and TR7 that
    are used to add new page table entries directly to TLB.
    This could be used to directly update TLB after a
    pagefault, so you wouldn't need a regular page table (it
    may be slower then normal pagetables and that is what I am
    going to measure).

    What I need is the MOV tr, ex instruction that fills tr6
    and tr7 with linear-to-physical address translation.
    Current Bochs response to this instruction is panic. The
    only part I found in IA Software Developper's Manual
    (24547203) that deals with test registers is a really small
    chapter (or better say paragraph) 17.18 in Volume 3. Almost
    all information I have is from two books written in slovak,
    but maybe there is more information about it in older intel
    486 documentation. As soon as I find it, I will post it
    here.

    On Pentium and later processors, there are no test
    registers. Instead, there are two MSRs with similar
    functionality. Again, no serious information found in intel
    documentation. I have found one file that briefly desribes
    these MSRs at
    http://www.cubic.org/source/archive/coding/assembly/special/
    msrlist.txt (MSRs 8 and 9). On P6, yet different MSRs are
    used. But one way of accessing TLB is just enough for me
    and it seems that the 486 way is the most simple.

    I am going to look at bochs sources to find out if I am
    able to add this as soon as I have some time, but first I
    will try to find some "good enough documentetion :)" and a
    real 486 to see how it exactly works.

     
  • Full MSR support integrated into Bochs - it is possible to configure MSRs you want for Bochs now.