From: Stefan E. <se...@us...> - 2002-07-25 14:21:45
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Update of /cvsroot/blob/blob/include/blob/arch In directory usw-pr-cvs1:/tmp/cvs-serv22593 Modified Files: system3.h Log Message: - split up cramfs.img in root and data filesystems Index: system3.h =================================================================== RCS file: /cvsroot/blob/blob/include/blob/arch/system3.h,v retrieving revision 1.17 retrieving revision 1.18 diff -u -d -r1.17 -r1.18 --- system3.h 13 May 2002 09:38:59 -0000 1.17 +++ system3.h 25 Jul 2002 14:21:42 -0000 1.18 @@ -30,8 +30,8 @@ #undef CPU_SPEED_133 /* SYSTEM3 with 64 MB SDRAM, all on bank0 */ -//#undef CONFIG_SYSTEM3_REV0802 -#define CONFIG_SYSTEM3_REV0802 +#undef CONFIG_SYSTEM3_REV0802 +//#define CONFIG_SYSTEM3_REV0802 /* boot CPU speed */ #ifdef CPU_SPEED_133 @@ -71,8 +71,10 @@ #define LOAD_RAMDISK 1 /* load ramdisk into ram */ #define RAMDISK_FLASH_BASE (0x00180000) #define RAMDISK_FLASH_LEN (1536 * 1024) -#define CRAMFS_FLASH_BASE (0x00300000) -#define CRAMFS_FLASH_LEN (13312 * 1024) +#define ROOTFS_FLASH_BASE (0x00300000) +#define ROOTFS_FLASH_LEN (0x00600000) /* 6M */ +#define DATAFS_FLASH_BASE (0x00900000) +#define DATAFS_FLASH_LEN (0x00700000) /* 7M */ /* system3 RAM pool for up/downloading */ #if !defined(CONFIG_SYSTEM3_REV0802) @@ -91,6 +93,13 @@ /* the size (in kbytes) to which the compressed ramdisk expands */ #define RAMDISK_SIZE (8 * 1024) +/* let SDRAM run at FULL memclk speed */ +#undef MDREFR_MEMCLK_FULLSPEED_0 +#undef MDREFR_MEMCLK_FULLSPEED_1 +#undef MDREFR_MEMCLK_FULLSPEED_2 +//#define MDREFR_MEMCLK_FULLSPEED_0 +//#define MDREFR_MEMCLK_FULLSPEED_1 +//#define MDREFR_MEMCLK_FULLSPEED_2 /* Memory configuration */ #ifdef BLOB_NEED_MEMCONFIG @@ -105,7 +114,6 @@ #define MSC0_VALUE_100_120 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(3) | MSC_RRR(2) #define MSC0_VALUE_100_100 MSC_RT_ROMFLASH | MSC_RBW32 | MSC_RDF(11) | MSC_RDN(3) | MSC_RRR(2) #define MSC1_VALUE_100 MSC_RT_ROMFLASH | MSC_RBW16 | MSC_RDF(5) | MSC_RDN(1) | MSC_RRR(1)| ((MSC_RT_VARLAT_345 | MSC_RBW16 | MSC_RDF(30) | MSC_RDN(30) | MSC_RRR(7))<<16) -//#define MSC2_VALUE_100 MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(9) | MSC_RDN(2) | MSC_RRR(1) #define MSC2_VALUE_100 MSC_RT_VARLAT_345 | MSC_RBW32 | MSC_RDF(13) | MSC_RDN(6) | MSC_RRR(3) #define MECR_VALUE_100 MECR_BSIO0(0x1f) | MECR_BSA0(0x1f) | MECR_BSM0(0x1f) | MECR_BSIO1(0x1f) | MECR_BSA1(0x1f) | MECR_BSM1(0x1f) |