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Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: William Cohen <wcohen@re...> - 2012-09-10 15:56

On 09/09/2012 05:03 PM, Dan Terpstra wrote:
> My bad.
> I added the new definitions of these events to the ivybridge table and copied the old definitions to the sandybridge table, but forgot to remove them from the combined sandy / ivy table. I checked in a fix. Give it another spin.
> - d
> 

Hi Dan,

Thanks for checking in the Intel Ivy Bridge fix.  An updated papi rpm with the patch is being made for Fedora rawhide.


http://koji.fedoraproject.org/koji/taskinfo?taskID=4472538

-Will

Thread View

Thread	Author	Date
[perfmon2] Event name differences between Intel Sandy Bridge and Ivy Bridge	William Cohen <wcohen@re...>

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: Vince Weaver <vweaver1@ee...> - 2012-08-31 18:35

On Thu, 30 Aug 2012, William Cohen wrote:

> Running ctests/multiplex1:PAPI Error: papi_preset: Error finding event BR_INST_R
> ETIRED:CONDITIONAL.
> PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.
> PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.

It looks like 

commit 54d7e8c70521717fce33dcd7a6a649b87e3b1e9f
Author: Stephane Eranian <eranian@...>
Date:   Sat Aug 4 02:00:08 2012 +0200

    make L2_RQSTS umasks more consistent
    
    RFO_HITS => RFO_HIT


and

commit aff07e5c925e6d1757bf4cbbec2be19497fd8255
Author: Stephane Eranian <eranian@...>
Date:   Sat Aug 4 01:54:06 2012 +0200

    Make some umasks names more consistent
    
    TAKEN_RETURN_NEAR => TAKEN_NEAR_RETURN
    ALL_CONDITIONAL => ALL_CONF
    
    looks more natural that way.

caused these changes.

It looks like IVB got updated and SNB did not.  We can change the PAPI 
papi_events.csv to use the new names, but unfortunately the 5.0 release 
has the old names which conflicts with the libpfm4.3 release's new names.

Vince

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: Dan Terpstra <terpstra@ee...> - 2012-08-31 18:44

Is this a candidate for resurrecting our patching protocol?
It'll only affect IvyBridge users with the new libpfm4.3, but that's becoming an increasingly large subset.
I suppose the patch could include libpfm4.3, but that'd make it pretty bulky :)
- d

On Aug 31, 2012, at 2:19 PM, Vince Weaver wrote:

> On Thu, 30 Aug 2012, William Cohen wrote:
> 
>> Running ctests/multiplex1:PAPI Error: papi_preset: Error finding event BR_INST_R
>> ETIRED:CONDITIONAL.
>> PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.
>> PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.
> 
> It looks like 
> 
> commit 54d7e8c70521717fce33dcd7a6a649b87e3b1e9f
> Author: Stephane Eranian <eranian@...>
> Date:   Sat Aug 4 02:00:08 2012 +0200
> 
>    make L2_RQSTS umasks more consistent
> 
>    RFO_HITS => RFO_HIT
> 
> 
> and
> 
> commit aff07e5c925e6d1757bf4cbbec2be19497fd8255
> Author: Stephane Eranian <eranian@...>
> Date:   Sat Aug 4 01:54:06 2012 +0200
> 
>    Make some umasks names more consistent
> 
>    TAKEN_RETURN_NEAR => TAKEN_NEAR_RETURN
>    ALL_CONDITIONAL => ALL_CONF
> 
>    looks more natural that way.
> 
> caused these changes.
> 
> It looks like IVB got updated and SNB did not.  We can change the PAPI 
> papi_events.csv to use the new names, but unfortunately the 5.0 release 
> has the old names which conflicts with the libpfm4.3 release's new names.
> 
> Vince
> 
> _______________________________________________
> Perfapi-devel mailing list
> Perfapi-devel@...
> http://lists.eecs.utk.edu/mailman/listinfo/perfapi-devel

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: Vince Weaver <vweaver1@ee...> - 2012-08-31 18:45

On Fri, 31 Aug 2012, Dan Terpstra wrote:

> Is this a candidate for resurrecting our patching protocol?
> It'll only affect IvyBridge users with the new libpfm4.3, but that's becoming an increasingly large subset.
> I suppose the patch could include libpfm4.3, but that'd make it pretty bulky :)

We included a libpfm git snapshot in the PAPI 5.0 release, so the bump up
to libpfm4.3 is small.  It's actually already included in PAPI git HEAD.

If we do a soonish PAPI 5.0.1 or similar, it would definitely make sense 
to include libpfm4.3.

I should update the PAPI git HEAD to have matching event names in 
papi_events.csv, but I want to see if the SNB names are going to change 
too before we split them out (IVB and SNB have shared event names 
currently)

Vince




> - d
> 
> On Aug 31, 2012, at 2:19 PM, Vince Weaver wrote:
> 
> > On Thu, 30 Aug 2012, William Cohen wrote:
> > 
> >> Running ctests/multiplex1:PAPI Error: papi_preset: Error finding event BR_INST_R
> >> ETIRED:CONDITIONAL.
> >> PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.
> >> PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.
> > 
> > It looks like 
> > 
> > commit 54d7e8c70521717fce33dcd7a6a649b87e3b1e9f
> > Author: Stephane Eranian <eranian@...>
> > Date:   Sat Aug 4 02:00:08 2012 +0200
> > 
> >    make L2_RQSTS umasks more consistent
> > 
> >    RFO_HITS => RFO_HIT
> > 
> > 
> > and
> > 
> > commit aff07e5c925e6d1757bf4cbbec2be19497fd8255
> > Author: Stephane Eranian <eranian@...>
> > Date:   Sat Aug 4 01:54:06 2012 +0200
> > 
> >    Make some umasks names more consistent
> > 
> >    TAKEN_RETURN_NEAR => TAKEN_NEAR_RETURN
> >    ALL_CONDITIONAL => ALL_CONF
> > 
> >    looks more natural that way.
> > 
> > caused these changes.
> > 
> > It looks like IVB got updated and SNB did not.  We can change the PAPI 
> > papi_events.csv to use the new names, but unfortunately the 5.0 release 
> > has the old names which conflicts with the libpfm4.3 release's new names.
> > 
> > Vince
> > 
> > _______________________________________________
> > Perfapi-devel mailing list
> > Perfapi-devel@...
> > http://lists.eecs.utk.edu/mailman/listinfo/perfapi-devel
> 
> 
> 

Vince
vweaver1@...

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: Dan Terpstra <terpstra@ee...> - 2012-09-06 20:56

I've committed a fix for these naming changes but haven't tested it because we don't have an Ivy Bridge.
Will, pull from git and give it a spin on an Ivy when you get a chance.
Thanks,
- d

On Aug 31, 2012, at 2:19 PM, Vince Weaver wrote:

> On Thu, 30 Aug 2012, William Cohen wrote:
> 
>> Running ctests/multiplex1:PAPI Error: papi_preset: Error finding event BR_INST_R
>> ETIRED:CONDITIONAL.
>> PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.
>> PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.
> 
> It looks like 
> 
> commit 54d7e8c70521717fce33dcd7a6a649b87e3b1e9f
> Author: Stephane Eranian <eranian@...>
> Date:   Sat Aug 4 02:00:08 2012 +0200
> 
>    make L2_RQSTS umasks more consistent
> 
>    RFO_HITS => RFO_HIT
> 
> 
> and
> 
> commit aff07e5c925e6d1757bf4cbbec2be19497fd8255
> Author: Stephane Eranian <eranian@...>
> Date:   Sat Aug 4 01:54:06 2012 +0200
> 
>    Make some umasks names more consistent
> 
>    TAKEN_RETURN_NEAR => TAKEN_NEAR_RETURN
>    ALL_CONDITIONAL => ALL_CONF
> 
>    looks more natural that way.
> 
> caused these changes.
> 
> It looks like IVB got updated and SNB did not.  We can change the PAPI 
> papi_events.csv to use the new names, but unfortunately the 5.0 release 
> has the old names which conflicts with the libpfm4.3 release's new names.
> 
> Vince
> 
> 
> ------------------------------------------------------------------------------
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> threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/
> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/perfmon2-devel

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: William Cohen <wcohen@re...> - 2012-09-07 15:12

Attachments: papi-ivb.patch

On 09/06/2012 04:56 PM, Dan Terpstra wrote:
> I've committed a fix for these naming changes but haven't tested it because we don't have an Ivy Bridge.
> Will, pull from git and give it a spin on an Ivy when you get a chance.
> Thanks,
> - d

Hi Dan,

I gave it a try this morning.  It improved the the output of the test results by eliminating the:

PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.


However, still see the the following messages:

 PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.

It also needed the attached patch to remove the  BR_INST_RETIRED:CONDITIONAL error.  The "papi_avail" is a quick way to test to check that the presets don't have any problems with the libpfm lookups. Below is the output of the "papi_avail" for papi git and the attached patch.

$ papi_avail
Available events and hardware information.
--------------------------------------------------------------------------------
PAPI Version             : 5.0.0.0
Vendor string and code   : GenuineIntel (1)
Model string and code    : Intel(R) Core(TM) i7-3610QM CPU @ 2.30GHz (58)
CPU Revision             : 9.000000
CPUID Info               : Family: 6  Model: 58  Stepping: 9
CPU Max Megahertz        : 2301
CPU Min Megahertz        : 1200
Hdw Threads per core     : 2
Cores per Socket         : 4
NUMA Nodes               : 1
CPUs per Node            : 8
Total CPUs               : 8
Running in a VM          : no
Number Hardware Counters : 11
Max Multiplex Counters   : 64
--------------------------------------------------------------------------------

    Name        Code    Avail Deriv Description (Note)
PAPI_L1_DCM  0x80000000  Yes   No   Level 1 data cache misses
PAPI_L1_ICM  0x80000001  Yes   No   Level 1 instruction cache misses
PAPI_L2_DCM  0x80000002  Yes   Yes  Level 2 data cache misses
PAPI_L2_ICM  0x80000003  Yes   No   Level 2 instruction cache misses
PAPI_L3_DCM  0x80000004  No    No   Level 3 data cache misses
PAPI_L3_ICM  0x80000005  No    No   Level 3 instruction cache misses
PAPI_L1_TCM  0x80000006  Yes   Yes  Level 1 cache misses
PAPI_L2_TCM  0x80000007  Yes   No   Level 2 cache misses
PAPI_L3_TCM  0x80000008  Yes   No   Level 3 cache misses
PAPI_CA_SNP  0x80000009  No    No   Requests for a snoop
PAPI_CA_SHR  0x8000000a  No    No   Requests for exclusive access to shared cache line
PAPI_CA_CLN  0x8000000b  No    No   Requests for exclusive access to clean cache line
PAPI_CA_INV  0x8000000c  No    No   Requests for cache line invalidation
PAPI_CA_ITV  0x8000000d  No    No   Requests for cache line intervention
PAPI_L3_LDM  0x8000000e  No    No   Level 3 load misses
PAPI_L3_STM  0x8000000f  No    No   Level 3 store misses
PAPI_BRU_IDL 0x80000010  No    No   Cycles branch units are idle
PAPI_FXU_IDL 0x80000011  No    No   Cycles integer units are idle
PAPI_FPU_IDL 0x80000012  No    No   Cycles floating point units are idle
PAPI_LSU_IDL 0x80000013  No    No   Cycles load/store units are idle
PAPI_TLB_DM  0x80000014  Yes   Yes  Data translation lookaside buffer misses
PAPI_TLB_IM  0x80000015  Yes   No   Instruction translation lookaside buffer misses
PAPI_TLB_TL  0x80000016  No    No   Total translation lookaside buffer misses
PAPI_L1_LDM  0x80000017  Yes   No   Level 1 load misses
PAPI_L1_STM  0x80000018  Yes   No   Level 1 store misses
PAPI_L2_LDM  0x80000019  No    No   Level 2 load misses
PAPI_L2_STM  0x8000001a  Yes   No   Level 2 store misses
PAPI_BTAC_M  0x8000001b  No    No   Branch target address cache misses
PAPI_PRF_DM  0x8000001c  No    No   Data prefetch cache misses
PAPI_L3_DCH  0x8000001d  No    No   Level 3 data cache hits
PAPI_TLB_SD  0x8000001e  No    No   Translation lookaside buffer shootdowns
PAPI_CSR_FAL 0x8000001f  No    No   Failed store conditional instructions
PAPI_CSR_SUC 0x80000020  No    No   Successful store conditional instructions
PAPI_CSR_TOT 0x80000021  No    No   Total store conditional instructions
PAPI_MEM_SCY 0x80000022  No    No   Cycles Stalled Waiting for memory accesses
PAPI_MEM_RCY 0x80000023  No    No   Cycles Stalled Waiting for memory Reads
PAPI_MEM_WCY 0x80000024  No    No   Cycles Stalled Waiting for memory writes
PAPI_STL_ICY 0x80000025  Yes   No   Cycles with no instruction issue
PAPI_FUL_ICY 0x80000026  No    No   Cycles with maximum instruction issue
PAPI_STL_CCY 0x80000027  No    No   Cycles with no instructions completed
PAPI_FUL_CCY 0x80000028  No    No   Cycles with maximum instructions completed
PAPI_HW_INT  0x80000029  No    No   Hardware interrupts
PAPI_BR_UCN  0x8000002a  Yes   Yes  Unconditional branch instructions
PAPI_BR_CN   0x8000002b  Yes   No   Conditional branch instructions
PAPI_BR_TKN  0x8000002c  Yes   Yes  Conditional branch instructions taken
PAPI_BR_NTK  0x8000002d  Yes   No   Conditional branch instructions not taken
PAPI_BR_MSP  0x8000002e  Yes   No   Conditional branch instructions mispredicted
PAPI_BR_PRC  0x8000002f  Yes   Yes  Conditional branch instructions correctly predicted
PAPI_FMA_INS 0x80000030  No    No   FMA instructions completed
PAPI_TOT_IIS 0x80000031  No    No   Instructions issued
PAPI_TOT_INS 0x80000032  Yes   No   Instructions completed
PAPI_INT_INS 0x80000033  No    No   Integer instructions
PAPI_FP_INS  0x80000034  No    No   Floating point instructions
PAPI_LD_INS  0x80000035  Yes   No   Load instructions
PAPI_SR_INS  0x80000036  Yes   No   Store instructions
PAPI_BR_INS  0x80000037  Yes   No   Branch instructions
PAPI_VEC_INS 0x80000038  No    No   Vector/SIMD instructions (could include integer)
PAPI_RES_STL 0x80000039  No    No   Cycles stalled on any resource
PAPI_FP_STAL 0x8000003a  No    No   Cycles the FP unit(s) are stalled
PAPI_TOT_CYC 0x8000003b  Yes   No   Total cycles
PAPI_LST_INS 0x8000003c  No    No   Load/store instructions completed
PAPI_SYC_INS 0x8000003d  No    No   Synchronization instructions completed
PAPI_L1_DCH  0x8000003e  No    No   Level 1 data cache hits
PAPI_L2_DCH  0x8000003f  Yes   Yes  Level 2 data cache hits
PAPI_L1_DCA  0x80000040  No    No   Level 1 data cache accesses
PAPI_L2_DCA  0x80000041  Yes   No   Level 2 data cache accesses
PAPI_L3_DCA  0x80000042  Yes   Yes  Level 3 data cache accesses
PAPI_L1_DCR  0x80000043  No    No   Level 1 data cache reads
PAPI_L2_DCR  0x80000044  Yes   No   Level 2 data cache reads
PAPI_L3_DCR  0x80000045  Yes   No   Level 3 data cache reads
PAPI_L1_DCW  0x80000046  No    No   Level 1 data cache writes
PAPI_L2_DCW  0x80000047  Yes   No   Level 2 data cache writes
PAPI_L3_DCW  0x80000048  Yes   No   Level 3 data cache writes
PAPI_L1_ICH  0x80000049  No    No   Level 1 instruction cache hits
PAPI_L2_ICH  0x8000004a  Yes   No   Level 2 instruction cache hits
PAPI_L3_ICH  0x8000004b  No    No   Level 3 instruction cache hits
PAPI_L1_ICA  0x8000004c  No    No   Level 1 instruction cache accesses
PAPI_L2_ICA  0x8000004d  Yes   No   Level 2 instruction cache accesses
PAPI_L3_ICA  0x8000004e  Yes   No   Level 3 instruction cache accesses
PAPI_L1_ICR  0x8000004f  No    No   Level 1 instruction cache reads
PAPI_L2_ICR  0x80000050  Yes   No   Level 2 instruction cache reads
PAPI_L3_ICR  0x80000051  Yes   No   Level 3 instruction cache reads
PAPI_L1_ICW  0x80000052  No    No   Level 1 instruction cache writes
PAPI_L2_ICW  0x80000053  No    No   Level 2 instruction cache writes
PAPI_L3_ICW  0x80000054  No    No   Level 3 instruction cache writes
PAPI_L1_TCH  0x80000055  No    No   Level 1 total cache hits
PAPI_L2_TCH  0x80000056  No    No   Level 2 total cache hits
PAPI_L3_TCH  0x80000057  No    No   Level 3 total cache hits
PAPI_L1_TCA  0x80000058  No    No   Level 1 total cache accesses
PAPI_L2_TCA  0x80000059  Yes   Yes  Level 2 total cache accesses
PAPI_L3_TCA  0x8000005a  Yes   No   Level 3 total cache accesses
PAPI_L1_TCR  0x8000005b  No    No   Level 1 total cache reads
PAPI_L2_TCR  0x8000005c  Yes   Yes  Level 2 total cache reads
PAPI_L3_TCR  0x8000005d  Yes   Yes  Level 3 total cache reads
PAPI_L1_TCW  0x8000005e  No    No   Level 1 total cache writes
PAPI_L2_TCW  0x8000005f  Yes   No   Level 2 total cache writes
PAPI_L3_TCW  0x80000060  Yes   No   Level 3 total cache writes
PAPI_FML_INS 0x80000061  No    No   Floating point multiply instructions
PAPI_FAD_INS 0x80000062  No    No   Floating point add instructions
PAPI_FDV_INS 0x80000063  Yes   No   Floating point divide instructions
PAPI_FSQ_INS 0x80000064  No    No   Floating point square root instructions
PAPI_FNV_INS 0x80000065  No    No   Floating point inverse instructions
PAPI_FP_OPS  0x80000066  No    No   Floating point operations
PAPI_SP_OPS  0x80000067  No    No   Floating point operations; optimized to count scaled single precision vector operations
PAPI_DP_OPS  0x80000068  No    No   Floating point operations; optimized to count scaled double precision vector operations
PAPI_VEC_SP  0x80000069  No    No   Single precision vector/SIMD instructions
PAPI_VEC_DP  0x8000006a  No    No   Double precision vector/SIMD instructions
PAPI_REF_CYC 0x8000006b  Yes   No   Reference clock cycles
-------------------------------------------------------------------------
Of 108 possible events, 44 are available, of which 11 are derived.

avail.c                                     PASSED

-Will

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: Dan Terpstra <terpstra@ee...> - 2012-09-09 21:03

My bad.
I added the new definitions of these events to the ivybridge table and copied the old definitions to the sandybridge table, but forgot to remove them from the combined sandy / ivy table. I checked in a fix. Give it another spin.
- d

On Sep 7, 2012, at 11:12 AM, William Cohen wrote:

> On 09/06/2012 04:56 PM, Dan Terpstra wrote:
>> I've committed a fix for these naming changes but haven't tested it because we don't have an Ivy Bridge.
>> Will, pull from git and give it a spin on an Ivy when you get a chance.
>> Thanks,
>> - d
> 
> Hi Dan,
> 
> I gave it a try this morning.  It improved the the output of the test results by eliminating the:
> 
> PAPI Error: papi_preset: Error finding event L2_RQSTS:RFO_HITS.
> 
> 
> However, still see the the following messages:
> 
> PAPI Error: papi_preset: Error finding event BR_INST_RETIRED:CONDITIONAL.
> 
> It also needed the attached patch to remove the  BR_INST_RETIRED:CONDITIONAL error.  The "papi_avail" is a quick way to test to check that the presets don't have any problems with the libpfm lookups. Below is the output of the "papi_avail" for papi git and the attached patch.
> 
> $ papi_avail
> Available events and hardware information.
> --------------------------------------------------------------------------------
> PAPI Version             : 5.0.0.0
> Vendor string and code   : GenuineIntel (1)
> Model string and code    : Intel(R) Core(TM) i7-3610QM CPU @ 2.30GHz (58)
> CPU Revision             : 9.000000
> CPUID Info               : Family: 6  Model: 58  Stepping: 9
> CPU Max Megahertz        : 2301
> CPU Min Megahertz        : 1200
> Hdw Threads per core     : 2
> Cores per Socket         : 4
> NUMA Nodes               : 1
> CPUs per Node            : 8
> Total CPUs               : 8
> Running in a VM          : no
> Number Hardware Counters : 11
> Max Multiplex Counters   : 64
> --------------------------------------------------------------------------------
> 
>    Name        Code    Avail Deriv Description (Note)
> PAPI_L1_DCM  0x80000000  Yes   No   Level 1 data cache misses
> PAPI_L1_ICM  0x80000001  Yes   No   Level 1 instruction cache misses
> PAPI_L2_DCM  0x80000002  Yes   Yes  Level 2 data cache misses
> PAPI_L2_ICM  0x80000003  Yes   No   Level 2 instruction cache misses
> PAPI_L3_DCM  0x80000004  No    No   Level 3 data cache misses
> PAPI_L3_ICM  0x80000005  No    No   Level 3 instruction cache misses
> PAPI_L1_TCM  0x80000006  Yes   Yes  Level 1 cache misses
> PAPI_L2_TCM  0x80000007  Yes   No   Level 2 cache misses
> PAPI_L3_TCM  0x80000008  Yes   No   Level 3 cache misses
> PAPI_CA_SNP  0x80000009  No    No   Requests for a snoop
> PAPI_CA_SHR  0x8000000a  No    No   Requests for exclusive access to shared cache line
> PAPI_CA_CLN  0x8000000b  No    No   Requests for exclusive access to clean cache line
> PAPI_CA_INV  0x8000000c  No    No   Requests for cache line invalidation
> PAPI_CA_ITV  0x8000000d  No    No   Requests for cache line intervention
> PAPI_L3_LDM  0x8000000e  No    No   Level 3 load misses
> PAPI_L3_STM  0x8000000f  No    No   Level 3 store misses
> PAPI_BRU_IDL 0x80000010  No    No   Cycles branch units are idle
> PAPI_FXU_IDL 0x80000011  No    No   Cycles integer units are idle
> PAPI_FPU_IDL 0x80000012  No    No   Cycles floating point units are idle
> PAPI_LSU_IDL 0x80000013  No    No   Cycles load/store units are idle
> PAPI_TLB_DM  0x80000014  Yes   Yes  Data translation lookaside buffer misses
> PAPI_TLB_IM  0x80000015  Yes   No   Instruction translation lookaside buffer misses
> PAPI_TLB_TL  0x80000016  No    No   Total translation lookaside buffer misses
> PAPI_L1_LDM  0x80000017  Yes   No   Level 1 load misses
> PAPI_L1_STM  0x80000018  Yes   No   Level 1 store misses
> PAPI_L2_LDM  0x80000019  No    No   Level 2 load misses
> PAPI_L2_STM  0x8000001a  Yes   No   Level 2 store misses
> PAPI_BTAC_M  0x8000001b  No    No   Branch target address cache misses
> PAPI_PRF_DM  0x8000001c  No    No   Data prefetch cache misses
> PAPI_L3_DCH  0x8000001d  No    No   Level 3 data cache hits
> PAPI_TLB_SD  0x8000001e  No    No   Translation lookaside buffer shootdowns
> PAPI_CSR_FAL 0x8000001f  No    No   Failed store conditional instructions
> PAPI_CSR_SUC 0x80000020  No    No   Successful store conditional instructions
> PAPI_CSR_TOT 0x80000021  No    No   Total store conditional instructions
> PAPI_MEM_SCY 0x80000022  No    No   Cycles Stalled Waiting for memory accesses
> PAPI_MEM_RCY 0x80000023  No    No   Cycles Stalled Waiting for memory Reads
> PAPI_MEM_WCY 0x80000024  No    No   Cycles Stalled Waiting for memory writes
> PAPI_STL_ICY 0x80000025  Yes   No   Cycles with no instruction issue
> PAPI_FUL_ICY 0x80000026  No    No   Cycles with maximum instruction issue
> PAPI_STL_CCY 0x80000027  No    No   Cycles with no instructions completed
> PAPI_FUL_CCY 0x80000028  No    No   Cycles with maximum instructions completed
> PAPI_HW_INT  0x80000029  No    No   Hardware interrupts
> PAPI_BR_UCN  0x8000002a  Yes   Yes  Unconditional branch instructions
> PAPI_BR_CN   0x8000002b  Yes   No   Conditional branch instructions
> PAPI_BR_TKN  0x8000002c  Yes   Yes  Conditional branch instructions taken
> PAPI_BR_NTK  0x8000002d  Yes   No   Conditional branch instructions not taken
> PAPI_BR_MSP  0x8000002e  Yes   No   Conditional branch instructions mispredicted
> PAPI_BR_PRC  0x8000002f  Yes   Yes  Conditional branch instructions correctly predicted
> PAPI_FMA_INS 0x80000030  No    No   FMA instructions completed
> PAPI_TOT_IIS 0x80000031  No    No   Instructions issued
> PAPI_TOT_INS 0x80000032  Yes   No   Instructions completed
> PAPI_INT_INS 0x80000033  No    No   Integer instructions
> PAPI_FP_INS  0x80000034  No    No   Floating point instructions
> PAPI_LD_INS  0x80000035  Yes   No   Load instructions
> PAPI_SR_INS  0x80000036  Yes   No   Store instructions
> PAPI_BR_INS  0x80000037  Yes   No   Branch instructions
> PAPI_VEC_INS 0x80000038  No    No   Vector/SIMD instructions (could include integer)
> PAPI_RES_STL 0x80000039  No    No   Cycles stalled on any resource
> PAPI_FP_STAL 0x8000003a  No    No   Cycles the FP unit(s) are stalled
> PAPI_TOT_CYC 0x8000003b  Yes   No   Total cycles
> PAPI_LST_INS 0x8000003c  No    No   Load/store instructions completed
> PAPI_SYC_INS 0x8000003d  No    No   Synchronization instructions completed
> PAPI_L1_DCH  0x8000003e  No    No   Level 1 data cache hits
> PAPI_L2_DCH  0x8000003f  Yes   Yes  Level 2 data cache hits
> PAPI_L1_DCA  0x80000040  No    No   Level 1 data cache accesses
> PAPI_L2_DCA  0x80000041  Yes   No   Level 2 data cache accesses
> PAPI_L3_DCA  0x80000042  Yes   Yes  Level 3 data cache accesses
> PAPI_L1_DCR  0x80000043  No    No   Level 1 data cache reads
> PAPI_L2_DCR  0x80000044  Yes   No   Level 2 data cache reads
> PAPI_L3_DCR  0x80000045  Yes   No   Level 3 data cache reads
> PAPI_L1_DCW  0x80000046  No    No   Level 1 data cache writes
> PAPI_L2_DCW  0x80000047  Yes   No   Level 2 data cache writes
> PAPI_L3_DCW  0x80000048  Yes   No   Level 3 data cache writes
> PAPI_L1_ICH  0x80000049  No    No   Level 1 instruction cache hits
> PAPI_L2_ICH  0x8000004a  Yes   No   Level 2 instruction cache hits
> PAPI_L3_ICH  0x8000004b  No    No   Level 3 instruction cache hits
> PAPI_L1_ICA  0x8000004c  No    No   Level 1 instruction cache accesses
> PAPI_L2_ICA  0x8000004d  Yes   No   Level 2 instruction cache accesses
> PAPI_L3_ICA  0x8000004e  Yes   No   Level 3 instruction cache accesses
> PAPI_L1_ICR  0x8000004f  No    No   Level 1 instruction cache reads
> PAPI_L2_ICR  0x80000050  Yes   No   Level 2 instruction cache reads
> PAPI_L3_ICR  0x80000051  Yes   No   Level 3 instruction cache reads
> PAPI_L1_ICW  0x80000052  No    No   Level 1 instruction cache writes
> PAPI_L2_ICW  0x80000053  No    No   Level 2 instruction cache writes
> PAPI_L3_ICW  0x80000054  No    No   Level 3 instruction cache writes
> PAPI_L1_TCH  0x80000055  No    No   Level 1 total cache hits
> PAPI_L2_TCH  0x80000056  No    No   Level 2 total cache hits
> PAPI_L3_TCH  0x80000057  No    No   Level 3 total cache hits
> PAPI_L1_TCA  0x80000058  No    No   Level 1 total cache accesses
> PAPI_L2_TCA  0x80000059  Yes   Yes  Level 2 total cache accesses
> PAPI_L3_TCA  0x8000005a  Yes   No   Level 3 total cache accesses
> PAPI_L1_TCR  0x8000005b  No    No   Level 1 total cache reads
> PAPI_L2_TCR  0x8000005c  Yes   Yes  Level 2 total cache reads
> PAPI_L3_TCR  0x8000005d  Yes   Yes  Level 3 total cache reads
> PAPI_L1_TCW  0x8000005e  No    No   Level 1 total cache writes
> PAPI_L2_TCW  0x8000005f  Yes   No   Level 2 total cache writes
> PAPI_L3_TCW  0x80000060  Yes   No   Level 3 total cache writes
> PAPI_FML_INS 0x80000061  No    No   Floating point multiply instructions
> PAPI_FAD_INS 0x80000062  No    No   Floating point add instructions
> PAPI_FDV_INS 0x80000063  Yes   No   Floating point divide instructions
> PAPI_FSQ_INS 0x80000064  No    No   Floating point square root instructions
> PAPI_FNV_INS 0x80000065  No    No   Floating point inverse instructions
> PAPI_FP_OPS  0x80000066  No    No   Floating point operations
> PAPI_SP_OPS  0x80000067  No    No   Floating point operations; optimized to count scaled single precision vector operations
> PAPI_DP_OPS  0x80000068  No    No   Floating point operations; optimized to count scaled double precision vector operations
> PAPI_VEC_SP  0x80000069  No    No   Single precision vector/SIMD instructions
> PAPI_VEC_DP  0x8000006a  No    No   Double precision vector/SIMD instructions
> PAPI_REF_CYC 0x8000006b  Yes   No   Reference clock cycles
> -------------------------------------------------------------------------
> Of 108 possible events, 44 are available, of which 11 are derived.
> 
> avail.c                                     PASSED
> 
> -Will
> 
> <papi-ivb.patch>

Re: [perfmon2] [Perfapi-devel] Event name differences between Intel Sandy Bridge and Ivy Bridge

From: William Cohen <wcohen@re...> - 2012-09-10 15:56

On 09/09/2012 05:03 PM, Dan Terpstra wrote:
> My bad.
> I added the new definitions of these events to the ivybridge table and copied the old definitions to the sandybridge table, but forgot to remove them from the combined sandy / ivy table. I checked in a fix. Give it another spin.
> - d
> 

Hi Dan,

Thanks for checking in the Intel Ivy Bridge fix.  An updated papi rpm with the patch is being made for Fedora rawhide.


http://koji.fedoraproject.org/koji/taskinfo?taskID=4472538

-Will