its correct that there is lots of work involved in generating RTL from IG.
also another issue I am facing is that not all VHDL constructs can be
easily mapped/translated to SystemC.
in order to generate complete RTL-code for a single parsed VHDL design, is
there a need to consider all the 4 graphs of zamia?
or only with IG it is sufficient to get all info related to a single IP?
currently I am trying to traverse each node of the graph to pick/choose
relevant info to re-construct the RTL.
this approach is very tedious -(
do you see can there be a better way than this?
e.g. zamia-parser itself outputting all info in an predefine (readable)
format on which TCL/Perl/Python script can work to generate the RTL.
On Thu, Nov 24, 2011 at 5:47 AM, Guenter Bartsch <
> On Wed, Nov 23, 2011 at 1:25 PM, Saif Abrar <syedsaifabrar@...>
> > hello Guenter,
> > is there any attempt/scenario of (re-)generating VHDL/Verilog RTL once a
> > VHDL design has been parsed by zamiacad?
> we had some attempts in that direction in the past and some bits and
> pieces of that code may still remain in the repositories (grep for
> various dump* functions in the code) - but nothing was every completed
> in any way.
> it would be interesting to dump IG back to VHDL or, much more relevant
> for end users, in Verilog - or the other way round, generate IG from
> Verilog and dump it in VHDL - unfortunately the more interesting and
> relevant such an effort gets for end-users, the more work is behind
> VHDL -> IG -> VHDL
> should be fairly easy - just a lot of (boring) work
> VHDL -> IG -> Verilog
> is easy for simple cases, still a lot of work and the devil is in the
> details - certain constructs probably have no direct counterpart in
> Verilog -> IG -> VHDL
> is the most work as one would have to implement Verilog eloboration first.