Hello Ivo --
I'm sorry that you're having issues with the patches.
The IBS_OPS_TAGGED event is actually a performance counter event (select
value 0x1CF) that measures the number of ops that are tagged by IBS when
IBS is enabled and operational. You're right -- it's not what you're looking
I hesitated to suggest OProfile since your questions dealt with the latest
kernel support for PMC/IBS via PERF. AMD CodeAnalyst for Linux is available
free of charge from developer.amd.com. CodeAnalyst includes a version of
OProfile which has the latest support for IBS. (I see that you're using a
an Opteron 6128 Magny-Cours.) CodeAnalyst is a tool that uses its modified
version of OProfile for data collection. The OProfile tools included with
the CodeAnalyst release may be used independently of the CodeAnalyst GUI.
Of source, the source is provided. :-)
There is an experimental feature in the CodeAnalyst version of OProfile which
captures and displays the "DC miss address", i.e., the data operand address
for DC miss events. This information is captured by the OProfile daemon and
is written to a file:
The information in the log file is displayed using calog_report:
calog_report -f ibs_dcmiss.log
Data collection is set up using the OProfile opcontrol command. You will
need to enable capture of DC miss addresses using the unit mask specified
for IBS op events, e.g.,
opcontrol --event=IBS_OP_ALL:250000:3:1:1 \
The OProfile events and unit_mask files have information about the
IBS event names and unit masks. The event files are in:
The "ibs_op" unit mask has the definition of the allowable unit mask values.
Please feel free to hack away at this experimental feature. The operand
addresses are logged in:
and the feature is initialized in:
You could always grep for "add_calog_data" or "init_calog". The code
for calog_report is in:
Collin McCurdy at Oak Ridge National Lab successfully hacked the OProfile
driver to capture this kind of IBS data. So, he may be another resource.
If you go the CodeAnalyst/OProfile route, I hope this information is helpful.
Thanks for being patient!
Dr. Paul Drongowski
Consultant at AMD
AMD Boston Design Center
From: Ivo Steinmann [mailto:isteinmann@...]
Sent: Tuesday, June 21, 2011 7:13 AM
Cc: Drongowski, Paul
Subject: Re: [perfmon2] AMD IBS Support
Thx for your answer.
Well, I tried to apply the IBS perf_event_open patches of Robert. But since these kernel patches are almost an year old, parts of them are not possible to apply because they are outdated. The strange thing is, that there's a lot of IBS code in the oprofile driver module. At least I can see that IBS works with oprofile, but I guess I can't use oprofile for my purposes.
The current libpfm4 reports only the IBS_OPS_TAGGED ibs event on my AMD Opteron 6128 machine. No idea what this event means. I guess I need the
libpfm4/examples# ./showevtinfo ibs
IDX : 134217846
PMU name : amd64_fam10h_istanbul (AMD64 Fam10h Istanbul)
Name : IBS_OPS_TAGGED
Equiv : None
Flags : None
Desc : IBS Ops Tagged
Code : 0x1cf
Modif-00 : 0x00 : PMU : [k] : monitor at priv level 0 (boolean)
Modif-01 : 0x01 : PMU : [u] : monitor at priv level 1, 2, 3 (boolean)
Modif-02 : 0x02 : PMU : [e] : edge level (boolean)
Modif-03 : 0x03 : PMU : [i] : invert (boolean)
Modif-04 : 0x04 : PMU : [c] : counter-mask in range [0-255] (integer)
Modif-05 : 0x05 : PMU : [h] : monitor in hypervisor (boolean)
Modif-06 : 0x06 : PMU : [g] : measure in guest (boolean)
Well, maybe I have to switch my project to Intel Nehalem architecture until this IBS stuff is usable/documented with libpfm4/perf_event_open.
Am 06.06.2011 15:57, schrieb Drongowski, Paul:
> Hello Ivo --
> Yep, you will need to use the AMD IBS feature.
> Sampling the performance monitoring counters (PMCs) is imprecise.
> When a PMC (overflow) generates an interrupt, the processing pipeline
> is most probably far beyond the actual instruction which caused the
> PMC (overflow) that triggers the sampling interrupt. Thus, it's not
> possible to capture the data operand address for instructions that access memory via PMC sampling.
> IBS has this capability. After the IBS hardware selects and tags an
> execution op for sampling, it records the precise IP and events for
> the op. The IP is the address of the parent x86 op. If the op is a
> load or store, the data operand address is captured, too.
> Robert is the right guy for software questions. (I'm doing hardware
> now. :-)
> -- pj
> Paul Drongowski
> Consultant at AMD
> -----Original Message-----
> From: Ivo Steinmann [mailto:isteinmann@...]
> Sent: Sunday, June 05, 2011 7:44 PM
> To: perfmon2-devel@...
> Subject: [perfmon2] AMD IBS Support
> Hello all
> I'm really new to all this performance monitoring stuff.
> I would like to monitor cache accesses on my amd64 phenom and opteron machine and I also would like to get the address that is accessed. So I tried DATA_CACHE_ACCESSES, REQUESTS_TO_L2, READ_REQUEST_TO_L3_CACHE.
> It's working so far as the events are raised (using sigaction mechanism).
> attr.wakeup_events = 1;
> attr.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_ADDR; //| PERF_SAMPLE_READ | PERF_SAMPLE_PERIOD;
> attr.sample_period = SMPL_PERIOD;
> attr.read_format = 0;//PERF_FORMAT_GROUP | PERF_FORMAT_ID |
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_TOTAL_TIME_RUNNING;
> But somehow the addr is allways zero (nil) :(
> I think I have to use the amd64 IBS stuff (I guess then an address is returned). I found this thread: http://lkml.org/lkml/2010/4/13/336 from Robert Richter. There he provides some patches for amd64 ibs support.
> And here an example for libpfm4: https://lkml.org/lkml/2010/10/18/329
> Are this patches obsolete? How can I use IBS with libpfm4?
> I'm using this kernel version:
> And libpfm4 from:
> Ivo Steinmann
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