Am Mo, 19.02.2007, 13:44, schrieb Clifford Wolf:
> Hi Stefan,
>> I currently don't know too much about Verilog. Do you mean something
>> similiar to the vhdl output for digital components?
> well - I've seen that qucs generates a vhdl file for digital simulation. I
> assume that it is also possible to export a digital design as vhdl file so
> it can be used in a digital design process (e.g. for FPGA synthesis).
Actually there is no explicite export function. But you can display
the VHDL code after a digital simulation pressing F6 (last netlist).
The file displayed is then ~/.qucs/netlist.txt (IIRC).
> However, I did not find the feature in current qucs. Is it planed but not
> implemented? Or ist it really a new idea?
See above. Do you think it is then still necessary?
> Actually I have learned VHDL as well as Verilog HDL but like Verilog HDL
> better so I'm doing my FPGA projects in Verilog. But in some cases it does
> make sense to draw a schematic instead of writing Verilog HDL code
> manually. I'd like to do this using qucs and then export Verilog code for
> the modules I've designed as schematics.
> The other thing is that I have seen that it is possible to use existing
> VHDL modules in qucs designs. It would be great to also have this feature
> for Verilog modules. The only problem I see here is what happens if one
> tries to mix VHDL and Verilog modules. Usually this is no problem at all
> for comercial EDA/HDL tools, but afaik there is no support for something
> like that in the free software tools.
> Using a VHDL <-> Verilog HDL converter would be an ungly but possible
> solution for that. However - It isn't that of a problem for me because I'm
> only using Verilog HDL anyways... ;-)
Currently we are using the "freehdl route" to perform digital simulations.
We generate a vhdl file, then compile the simulator, run the simulator,
then evaluate the vcd output for displaying results.
Something similiar is then needed for verilog hdl. A well supported
simulator and appropiate interfaces, etc.
Just play around a bit with the vhdl stuff (also vhdl source code can
be edited and imported). Probably you find it even more convenient to
learn from the workbook chapter by mike brinson: