On Jan 20, 2008 6:42 AM, Stefan Jahn <stefan@...> wrote:
> Am Sa, 19.01.2008, 06:46, schrieb Gopala Krishna:
> > Hi ,
> > More doubts follow.
> > *) Regarding wire labels, is it possible to use only the internally
> > generated names for nodes and use wire labels only as an alias ?
> > For eg consider a resistor R1 which has two wire label's for its two
> > ports say "a" and "b".
> > If there weren't to the wire labels then the ports would have had the
> > names "_net0" and "_net1".
> > My idea is to use "net0", "_net1" ... *always* for the port/node
> > names. The wire label should act just as an alias. "a" will be alias
> > for "_net0" and "b" for "_net1" in above case while "_net0" and
> > "_net1" only goes to netlist. The aliasing can be later handled in
> > diagrams.
> > What do you have to say about this ?
> I don't know if this is a good idea. You won't then
> find a connection between the schematic and the netlist...
> Also it produces extra work in the alias handling.
> Why do you propose that?
Well now i realize aliasing becomes difficult if multiple ports are
allowed to have same port name. (i had thought this to be bug before
So preserving the idea of 0.0.14 qucs, what i could find out was, the
nodes/ports are enumerated only while generating netlist (on
simulation). That means the ports are re-enumerated every time
simulation is done. (Correct me if i am wrong)
Will this strategy work instead (is there any special reason for above ? )
While any component is placed, or connected the ports of the
components are enumerated then and there only.
That is node/port names are generated only once (or changes only when
connection to this node changes).
I now got to learn a bit on how sub circuits and library components
work. Wow! netlist generation code isn't that straight forward to
It is good if we to discuss a lot before the actual netlist generation
@Stefan and Michael: Is it possible for you people to outline the
netlist generation process ?
Also i could see that the default node naming scheme uses _net<x>
while digital nodes use net_net<x> instead. Can we use the latter one
( reference Schematic::throughAllNodes )
Finally is nodeset only used when intial voltage is set for that node ?
> > *) Secondly i discovered how to use widgets on graphicsview canvas, so
> > i was thinking of using QTableWidget to represent "Tabular diagram" as
> > well as "Truth table". But the caveat of this approach is widgets are
> > untransformable and hence they can't be scaled.
> > do you you feel widget approach can be used ?
> > (by making other diagrams also to be untransformable to maintain
> > uniformity)
> The unscalability is a no-go, isn't it?
Yeah but if scalability of diagrams isn't used then work gets simplified.
But anyway i'll implement it according to graphicsview framework
itself as the 0.0.14.
Gopala Krishna A