Das U-Boot - Universal Bootloader

Dear Wang Cheng,

in message <47429467b4.467b447429@...> you wrote:
> 
>    Thank you .
>    I'm porting U-Boot to the WindRiver MDP8xx PRO board.Now I think I
> should run the U-Boot on my board in the simpliest way, so I just
> configed the necessary devices like FLASH ,DRAM .
>    I can provide anything I have ,and thank you very very much .The
> include/configs/windriver.h and board/windrive/windriver.c have been
> included in the attachment.The MDP8xx PRO UM is too large to be
> attatched here.

So what do you expect?

You don't provide  any  information  about  the  hardware,  and  some
fragments  of  code  -  do  you by any chance expect that now sombody
volunteers and ports U-Boot to that board, based on zero information,
and for free?


I'm afraid it doesn't work like that.

Please make yourself clear and tell us what you want: on this mailing
list you can get free advice to solve specific problems etc., but  if
you  are  looking for someone who ports U-Boot to your board you will
either have to do it yourself or ask for professional support  (which
is _not_ free).

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@...
A penny saved is a penny to squander.
- Ambrose Bierce

Dear Muhammad,

in message <8529B5552D4EAA4DAEDF49650C64B2B4371366@...> you wrote:
>
> I want to add FTP support in u-boot for MPC8270 based system. Was there

Are you really sure you want FTP, not TFTP?

TFTP is already there, just use it.

For FTP you will need a full-blown TCP/IP stack. This  is  a  lot  of
work, and little benefit over TFTP.

> any work done on this front?? 

TFTP yes, FTP no.

Best regards, and a Happy New Year!

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@...
It is easier to write an incorrect program than understand a  correct
one.

In message <1538.81.227.175.195.1076440809.squirrel@...> you wrote:
>
> I built u-boot 1.0.1 with the new MontaVista Professional Edition 3.1, Dev
> Rocket Environment. It went well and I succeeded to flash the code to a
> Motorola Evaluation board ( PQ2FADS-VR ). However, when I tried to debug
> the code I started in start.S but after the the first jump bl in start.S I
> ended up in a C file that is handling U-boot CLI commands...

Can you prove this with a log of the exact steps you performed?

> I think that the GDB in BDI2000 is a 5.x version and GDB in the MontaVista
> Professional Edition 3.1 is a 6.0 version ( Gcc 3.3.2 ).

There is no "GDB in  BDI2000".  The  BDI2000  implements  GDB  remote
protocol   over   TCP/IP.   This  protocol  is  pretty  much  version
independent.

> Do you think that this could be a possible issue or is it only me doing
> some configuration faults?

I guess the later is the case.

Best regards,

Wolfgang Denk

-- 
See us @ Embedded World, Nuremberg, Feb 17 - 19,  Hall 12.0 Booth 440
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@...
What is mind?  No matter.  What is matter?  Never mind.
                                      -- Thomas Hewitt Key, 1799-1875

John-

Arabella software has done a build of U-Boot for the Motorola MPC885ADS
board.  I have a working binary from Arabella.  I am in the process of
building my own adaptation for our hardware; the  DUET_ADS_config in the
current release version is supposed to build for the MPC885ADS.

Alan J. Luse
Embedded Systems Engineer
Time America, Inc.
51 West Third Street, Suite 310
Tempe, AZ 85281
Voice:  (480) 296-0408
Fax:  (480) 296-0444


-----Original Message-----
From: u-boot-users-admin@...
[mailto:u-boot-users-admin@...] On Behalf Of Kerl,
John
Sent: Friday, 16 April 2004 2:30 PM
To: u-boot-users@...
Subject: [U-Boot-Users] (no subject)


Is anyone starting work on 885 support?  We have an 885 board coming up
very soon, so I will be happy to help out.


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hi,

i am using smc driver for blackfin processor. it working fine. i am not =
sure of the question u have asked.
i mean, i havent done any change other than what has been released by =
you. i havent added any init in eth.c

regards
vidya

-----Original Message-----
From: u-boot-users-admin@...
[mailto:u-boot-users-admin@... Behalf Of Wolfgang
Kanovsky
Sent: Thursday, May 13, 2004 9:37 PM
To: U-Boot-Users
Subject: [U-Boot-Users] (no subject)
Importance: High



Hi
anyone here who knows how the CONFIG_DRIVER_SMC91111  is used ..when the
chip is on the ISA - BUS

mean it is not in the eth.c file for init ( i have configured it in the
board.h file ...)?

greets
Wolfgang K.



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In message <207EE0F3DFEED4119B0100508B441B36015864C1@....=
com> you wrote:
>=20
> (no subject)

Please always provide a meaningful subject when  posting  to  mailing
lists.

> For our custom board, based on AT91RM9200, we wants to use
> u-boot as a Linux bootloader.  We do not want to use any
> commercial software and hardware tools to program it.  We

No tools, he? Why do you want to make your life painful?

> u-boot to serial flash.  It is a two step process, first load
> an application called 'romboot.bin' then load the u-boot.  It
> seems 'romboot.bin' does preliminary set up, to load the u-boot

> image to serial flash.  The 'romboot.bin' image is built
> for the Atmel board.

... and is what you would probably call "commercial software"  ("pro-
prietary" or "non-free" are probably better desriptions).

> 1.
> Can I get the sources of this 'romboot.bin' or of similar
> program, that can be built with GNU tools of ARM?

Not here. Feel free to ask Atmel.

> 2.
> A Metrowerks project of 'romboot.bin' is available, but it uses
> some libraries (for example to have printf and scanf etc.) which

Feel free to ask Metrowerks, then.

> are not included in the project.  Is there any way I can compile
> it with GNU tools to make the complete application of
> 'romboot.bin'?

This is off topic here.

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@...
"Unibus timeout fatal trap program lost sorry"  -  An  error  message
printed by DEC's RSTS operating system for the PDP-11

In message <E1CBk2d-0000cF-Uu@...> you wrote:
> aGVsbG8gZXZlcnlvbmUgDQogICAgIGkgaGF2ZSBzb21lIHF1ZXN0aW9uIGFib3V0IHUtYm9=
vdA0K
> ICAgICAgMaGiaW4gdGhlIGNvbmZpZ3VyYXRpb25zICAgd2hhdCBtZWFucyBvZiBLR0RCIGJ=
hdWRy
> YXRlID8NCiAgICAgIDKhomluIHRoZSAgZXA3MzEyLmggIGF1dGhvciBkZWZpbmVkIHNvbWU=
gY29u
> ZmlndXJhdGlvbiBzdWNoIGFzIENGR19MT0FEX0FERFIsIGkgZm91bmQgdGhlc2UgY29uZml=
ndXJh
> dGlvbiBhcmVuJ3QgZGVmaW5lZCBpbiB0aGUgcmVhZG1lIHRoYXQgdGVsbHMgbWUgaG93IHR=
vIGRl
> ZmluZSBjb25maWd1cmF0aW9uLg0KICAgICAgDQoNCgkNCg0KoaGhoaGhoaGhoaGhoaGhodb=
CDQrA
> 8aOhDQogCQkJCQ0KDQqhoaGhoaGhoaGhoaGhoaGhzuKx+A0KoaGhoaGhoaGhoaGhoaGhoXN=
kdXN0
> aGQyMDAwQHlhaG9vLmNvbS5jbg0KoaGhoaGhoaGhoaGhoaGhoaGhoaEyMDA0LTA5LTI3DQo=
=3D


Please do not send base 64 encoded messages.

Please do not send HTML messages.

Please send plain text only.

Message unreadable, ignored. Sorry.

In message <24857.212.50.56.195.1097168150.squirrel@...> you wrote:
> 
> Does u-boot communicate with any hardware on PCI bus without using
> interrupts. Is this the common way for u-boot (I mean u-boot ports for
> different architectures, especially comparing with prort for the mpc824x
> arch.).

Normally U-Boot uses polled drivers only,  i.  e.  it  does  not  use
interrupts.

> By the way, I have to say that leds on the ethernet card did never blink
> under u-boot. (Obviously it is running/blinking on some other Linux PC's).
> Does it mean something informative (except that it doesn't work)...

It may mean anything. For example,  you  might  have  missed  to  add
DC2114x support to your configuration file.


Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-4596-87  Fax: (+49)-8142-4596-88  Email: wd@...
If I don't document something, it's usually either for a good reason,
or a bad reason.  In this case it's a good reason.  :-)
                 - Larry Wall in <1992Jan17.005405.16806@...>

In message <20050131121836.10368.qmail@...> you wrote:
> 
>   =0Ahello all,=0Ai am new to embedded systems.=0Ai am trying to build a to=
> ol chain using binutils-2.14, gcc-3.3.2, glibc-2.3.2. All are downloaded fr=
> om kegel.com.=0A=0Ai built successfully the binutils.=0Awhen i trying to bu=
> ilt the gcc, i face the errors.=0Ai configured gcc using the following comm=

Please learn netiquette.

First provide a meaningful subject.

Then fix your mailer to post plaintext only.

Then find a mailing list where your request might be on topic.


This is the U-Boot mailing list. Your question is absolutely off topic here.

> --Next_1107173915---0-203.199.83.32-10234
> Content-type: text/html;
> 	charset=iso-8859-1
> Content-Transfer-Encoding: quoted-printable
> Content-Disposition: inline
> 
> <P>=0A&nbsp; <BR>=0Ahello all,<BR>=0Ai am new to embedded systems.<BR>=0Ai =
> am trying to build a tool chain using binutils-2.14, gcc-3.3.2, glibc-2.3.2=

And NEVER post HTML to this list.


Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
The high cost of living hasn't affected its popularity.

In message <4bdc54b005020705577ecf6861@...> you wrote:
> 
> i'm starting to use u-boot for the first time. But i encounter a lot
> of dificulties.

I see. It seems your first problem is that you don't understand  how
to enter a subject in the mailer?

> The first problem is that i can't find my evaluation board in config
> files. how i can build u-boot withou this file?

If ther eis no config file, then there is probably no  port  yet.  In
this case you will have to port U-Boot.

> Need i to write my board configuration?

Yes, and all the rest which is necesary to complete a port.

> what memery is needeed to uboot? i want to put it in flash memory.

memery = memory? U-Boot needs some ROM (flash is fine) and RAM to run.

> i want to load linux via Ethernet and write into Flash memory, how i do it?

Read the manual and the FAQ.

> Thanks to give me some explanations, because english is not my
> language, and it is very difficult to find documentations in french.

We will try to help independent of your language skills. However, you
_are_ supposed to read the documentation (README, manual,  FAQ).  And
before posting.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
Peace was the way.
	-- Kirk, "The City on the Edge of Forever", stardate unknown

I used it about a year ago with NAND flash.  For NOR the usage is a bit
less compelling.  As the scan time is slow, you end up using an extra
partition for it anyway to keep the time down...might have almost been
in raw at that point for nor.  Yaffs may be useable now for nand, but
don't think anyone has ported it in at the loader yet...

Some of the upsides is you can update using nice file based things at
the kernel level if jffs is there, and if you have the time to wait on
boot, then you can put it all in a big partition.

Regards,
Richard W.

> -----Original Message-----
> From: u-boot-users-admin@... [mailto:u-boot-users-
> admin@...] On Behalf Of C.Michael Sundius
> Sent: Thursday, March 31, 2005 4:32 PM
> To: u-boot-users@...
> Subject: [U-Boot-Users] (no subject)
>=20
> Hi,
>=20
> sorry to be a pest,  A while ago I posted a message asking about
> support for JFFS2 within U-boot.
>=20
> I didn't get a response so I'm wondering if anyone uses this feature?
> in reading the code, it seems
> as though there are many comments indicating that the support is a
> "less than elegant" implementation.
> (to be more specific they say have a paper bag ready in case you have
> to puke :]
>=20
> that said, does anyone use this feature.. it seems to me that it is
> very useful to have and many would
> want it.. on the other hand I know that the JFFS2 people have moved
> forward and don't support older
> kernels and thus maybe this code is out of date.. or (more likely) my
> kernel is out of date.
>=20
> anyway, if anyone who has some experience with using JFFS2 in concert
> w/ u-boot could respond,
> I would be very grateful
>=20
> btw: the problems I am having seem to be related to reading symbolic
> links.
>=20
> thanks for you help
>=20
>=20
>=20
> C Michael Sundius
> Solico Group LLC
> 232 Nevada St
> San Francisco, CA 94110
> msundius@...
> (415)608-0121
>=20
>=20
>=20
> -------------------------------------------------------
> This SF.net email is sponsored by Demarc:
> A global provider of Threat Management Solutions.
> Download our HomeAdmin security software for free today!
> http://www.demarc.com/info/Sentarus/hamr30
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users@...
> https://lists.sourceforge.net/lists/listinfo/u-boot-users

repl: bad addresses:
	C.Michael Sundius <msundius@...> -- no at-sign after local-part (Sundius)


FIX YOUR MAILER!!!!



In message <0a998cc8d476962de3099ffa36976db3@...> you wrote:
> 
> what kernel do you use? what version of jffs?

No. This is useless. Don't ask for a  list  of  50  different  kernel
versions with 30 different versions of MTD code which are all wokring
in any combination.

Provide some useful, reproducable information yourself.


Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
A stone was placed at a ford in a river with the inscription:
"When this stone is covered it is dangerous to ford here."

In message <200505111412.AA28574024@...> you wrote:
> When I fire up the board,the U-boot reports are as follows:
...
> U-Boot 1.1.2 (May 10 2005 - 08:54:34)                                     
> 
> CPU:   MPC5200 v1.2 at 396 MHz                              
>        Bus 132 MHz, IPB 66 MHz, PCI 33 MHz                                          
> Board: Motorola MPC5200 (IceCube)                                 
> I2C:   85 kHz, ready                    
> DRAM:  32 MB            
> FLASH:  0 kB            
^^^^^^^^^^^^^^
Problem here

> **********************************************************
> Is it ok? What's the problem on "FLASH:  0 kB            
> *** Warning - bad CRC, using default environment     "?
> It can not find my flash on board?

Correct. Seems you don't have an IceCube (aka  Lite5200)  board.  You
will have to port U-Boot to your hartware.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
... bacteriological warfare ... hard to believe we were once foolish
enough to play around with that.
	-- McCoy, "The Omega Glory", stardate unknown

In message <200505111617.AA27328618@...> you wrote:
> Yes! My board has the different flash from icecube.Pls tell me which file I have to verify to make U-boot find my flash?

The flash driver in your board directory.

Ummm... you did rad the README, didn't you? Maybe you want to read it
again.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
"He was so narrow minded he could see through  a  keyhole  with  both
eyes ..."

In message <C54B5772-835F-47B2-87A3-D528D722C511@...> you wrote:
> 
> Here's a patch which puts the PHYs for the 3rd and 4th eTSECS into  
> RGMII mode on the 8548 CDS.

This patch does not apply any more against current sources.  Can  you
please verify which parts are still relevant, and resubmit?

Thanks.

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
A good aphorism is too hard for the tooth of time, and  is  not  worn
away  by  all  the  centuries,  although  it serves as food for every
epoch.                                  - Friedrich Wilhelm Nietzsche
                          _Miscellaneous Maxims and Opinions_ no. 168

Dear Cliff,

your port of U-Boot for the pxa255_idp has been broken since  it  was
added,  without  any  patches  /  fixes  in  my  queue? Are you still
maintaining this board? Or is it broken and orphaned  and  should  be
removed?

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
About the use of language: it is impossible to sharpen a pencil  with
a  blunt  ax.  It is equally vain to try to do it with ten blunt axes
instead.                                           -- Edsger Dijkstra

In message <OFEB63BC56.1BE20D74-ON4825711C.004474B1@...> you wr=
ote:
>
>        Where is the code about:=20
>           SMC1 Register (SMCMR)Setting;
>           SCC1 Registers(GSMR_L,DSR and so on.) Setting;
>           FEC  Register(SDCR) Setting;
>=20
>           PAPAR,PCPAR and PDPAR Setting;

May I suggest that you use tools like grep to search the source code?

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
Clothes make the man. Naked people have little  or  no  influence  on
society.                                                 - Mark Twain

In message <NEBBKBLAILPMPGBGOPJLAEFLGNAA.jerry@...> you wrote:
> Recently, I acquired a few surplus boards from a defunct product for
> the home entertainment industry.  The boards have an IBM PowerPC
> 405GP,support for DRAM, PCI bus cards and an onboard IDE controller
> (Promise PDC20265) as well as serial and Ethernet I/O.  The board
> originally has PPCBoot firmware (see attachment at end of this email
> for details).

I suggest you ask the manufacturer of these boards for the PPCboot source=
s. They must be available (GPL).

> configuring U-Boot for the board.  (Or if someone recognizes the board
> and could tell me a valid model configuration to use, so much
> better --Silk screen information says "Digital Home Technologies". ).

That's not much of information.

> I am new to ELDK, PPC, and Linux, so I need pointers to how to
> proceed.  I wonder if the interrupts for the IDE controller are

In general U-Boot does not use interrupts.

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
"In matters of principle, stand like a rock;  in  matters  of  taste,
swim with the current."                            - Thomas Jefferson

In message <003701c64800$f989b7f0$091a1bac@...> you wrote:
>=20
> This patch add a utility to download the image through a bdm ti the
> avnet5282 board.

This is the same patch as you sent before, under a different  subject
and desrciption.

Rejected, too.

Please be more careful what you post!

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
Documentation is like sex: when it is good, it is  very,  very  good;
and when it is bad, it is better than nothing.         - Dick Brandon

Dear Peter,

please provide a *descriptive* Subject next time. And ask  short  and
simple  questions  instead  of  posting  hundrets  of  lines of ighly
specific stuff which nobody will read. Maybe you should (re-) read
http://www.catb.org/%7eesr/faqs/smart-questions.html

N message <007601c67085$77b32bf0$3b8119ac@...> you wrote:
>=20
> I=92ve added in board definition into it and modified the default MPC85=
60ADS
> configuration for it.=A0 I have been able to burn it into flash on the =
> board,

What makes you think the MPC8560ADS would be a good starting point?

> The board I=92ve been given is very bare.=A0 It has 256 MByte DDR Main =
> RAM,=A0 32
> MByte Flash (64k sectors), Ethernet on MII, and Serial on SCC1.=A0 > No=
thing
> else on it.

I bet this is wrong. There are probabnly ten times more components on
your board which you did not mention that there are you did.

> This board use to run VxWorks so I took most of the settings used for >=
 that
> and modified U-boot as following (I hope someone can tell me if I did
> something wrong)

No. How could we? We have absolutely no idea what your hardware looks lik=
e.

> Anyone have any idea on what I=92ve done wrong?=A0 Are there any other =
board
> definitions in U-Boot I could use that might meet what I have better?

How could we without even having the slightest ideas of what you have?

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
panic: kernel trap (ignored)

Hello,

	I've had a similar problem when booting an MPC8541E custom board.
	It was caused by having configured 2 chipselects only 32K apart
	(which should be supported). Changed to have 64K separation and
	the problem went away. I've never investigated the issue further.

	Best Regards


-----Original Message-----
From: u-boot-users-admin@... =
[mailto:u-boot-users-admin@...] On Behalf Of Peter =
Wright
Sent: sexta-feira, 5 de Maio de 2006 21:50
To: u-boot-users@...
Subject: [U-Boot-Users] (no subject)

I have a custom MPC8560 Board that I've been told to get U-Boot working =
on.

I've added in board definition into it and modified the default =
MPC8560ADS
configuration for it.=A0 I have been able to burn it into flash on the =
board,
and step through it.=A0 U-Boot boots up and configures the TLB and then =
jumps
to the proper place in FLASH to continue the load.=A0 But it seems to go =
off
into the middle of nowhere when it comes to the serial_puts command.=A0 =
From
the JTAG and using the memory map that U-Boot compile makes it gets into =
the
serial_puts function and then jumps off into main memory for some =
reason.=A0
It then halts at where the debugger says is an invalid opcode.

Has anyone seen these sorts of problems before?

In message <E7E846FF4F1FE947AABFF850350820780CC09B@...=
MENS.NET> you wrote:
>=20
> 	Hello,
>=20
> 	I've had a similar problem when booting an MPC8541E custom board.
...
> -----Original Message-----


Grrrrgh.. No subject, even though replying to a previous message, and
top-post/full-quote?

PLEASE read the netiquette, see
http://www.netmeister.org/news/learn2quote.html

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
If a man had a child who'd gone  anti-social,  killed  perhaps,  he'd
still tend to protect that child.
	-- McCoy, "The Ultimate Computer", stardate 4731.3

Stefan,

Actually > 256MB won't work correctly.  There is a problem in
board/amcc/ocotea/init.S:

tlbtab:
    tlbtab_start
    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I)
    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1,
AC_R|AC_W|SA_G|SA_I)
    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0,
AC_R|AC_W|AC_X )
    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I
)
    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3,
AC_R|AC_W|SA_G|SA_I )
    tlbtab_en

The line:
=20
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )

...should be...

tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
                                                ^
------------------------------------------------^

The way it currently stands virtual addresses 256-512MB are mapped into
the same region as the 1st 256MB of SDRAM.

Marc Howard


> -----Original Message-----
> From: u-boot-users-bounces@...
> [mailto:u-boot-users-bounces@...] On Behalf=20
> Of Stefan Roese
> Sent: Thursday, September 28, 2006 5:48 AM
> To: u-boot-users@...
> Subject: Re: [U-Boot-Users] (no subject)
>=20
> Hi Gerald,
>=20
> On Thursday 28 September 2006 04:03, Gerald Jackson wrote:
> > Does anyone know why u-boot 1.1.4 fails if you use two dimms in the
> > Ocotea Amcc board?
> >
> > I have try two 256 dimm, two 512 dimm, and one 256 dimm in=20
> the second
> > slot ( nothing in the first slot) it all fails.
> >
> > Is this a know problem with the Ocotea board?
>=20
> No. IIRC, we have tested Ocotea with different DIMM modules.=20
> Which U-Boot=20
> version are you using? What DIMM modules are you using? And=20
> what combination=20
> _is_ working?
>=20
> A quick look at the TLB setup shows me, that a maximum of=20
> 512MBytes could be=20
> working. For more at least the TLB setup has to be changed.
>=20
> Best regards,
> Stefan
>=20
> --------------------------------------------------------------
> -----------
> Take Surveys. Earn Cash. Influence the Future of IT
> Join SourceForge.net's Techsay panel and you'll get the=20
> chance to share your
> opinions on IT & business topics through brief surveys -- and=20
> earn cash
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&CID=3DDEVDEV
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users@...
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>=20

Hi Marc,

On Thursday 28 September 2006 23:07, Howard, Marc wrote:
> Actually > 256MB won't work correctly.  There is a problem in
> board/amcc/ocotea/init.S:

<snip>

> The line:
>
> tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
> AC_R|AC_W|AC_X|SA_G|SA_I )
>
> ...should be...
>
> tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0,
> AC_R|AC_W|AC_X|SA_G|SA_I )
>                                                 ^
> ------------------------------------------------^
>
> The way it currently stands virtual addresses 256-512MB are mapped into
> the same region as the 1st 256MB of SDRAM.

Yes, you are right. Thanks. I will fix this in a few days and add some more 
tlb's to supports at least 512MB.

Best regards,
Stefan

Here is the error I get if I use the second DIMMS

U-Boot 1.1.4 (Jul 18 2006 - 07:36:20)

CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
MHz)
       I2C boot EEPROM enabled
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  ERROR: Cannot determine a common read delay.
### ERROR ### Please RESET the board ###

Gerald
=20
=20
-----Original Message-----
From: Gerald Jackson=20
Sent: Friday, September 29, 2006 6:16 PM
To: Marc.Howard@...; sr@...;
u-boot-users@...
Subject: Re: [U-Boot-Users] (no subject)

Marc,

After you make that change you can use both dimms slot on the ocotea
board?

What error did you receive before the modification?

if I use only the second dimm slot with 256M it errors. if I use the
first dimm slot it is ok and if I use both dimms slot it error as well.


I am using 1.1.4.

Gerald

-----Original Message-----
From: "Howard, Marc"<Marc.Howard@...>
Sent: 9/28/06 5:06:26 PM
To: "Stefan Roese"<sr@...>,
"u-boot-users@...>
Subject: Re: [U-Boot-Users] (no subject)

Stefan,

Actually > 256MB won't work correctly.  There is a problem in
board/amcc/ocotea/init.S:

tlbtab:
    tlbtab_start
    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I)
    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1,
AC_R|AC_W|SA_G|SA_I)
    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0,
AC_R|AC_W|AC_X )
    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I
)
    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3,
AC_R|AC_W|SA_G|SA_I )
    tlbtab_en

The line:
=20
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )

...should be...

tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
                                                ^
------------------------------------------------^

The way it currently stands virtual addresses 256-512MB are mapped into
the same region as the 1st 256MB of SDRAM.

Marc Howard


> -----Original Message-----
> From: u-boot-users-bounces@...
> [mailto:u-boot-users-bounces@...] On Behalf=20
> Of Stefan Roese
> Sent: Thursday, September 28, 2006 5:48 AM
> To: u-boot-users@...
> Subject: Re: [U-Boot-Users] (no subject)
>=20
> Hi Gerald,
>=20
> On Thursday 28 September 2006 04:03, Gerald Jackson wrote:
> > Does anyone know why u-boot 1.1.4 fails if you use two dimms in the
> > Ocotea Amcc board?
> >
> > I have try two 256 dimm, two 512 dimm, and one 256 dimm in=20
> the second
> > slot ( nothing in the first slot) it all fails.
> >
> > Is this a know problem with the Ocotea board?
>=20
> No. IIRC, we have tested Ocotea with different DIMM modules.=20
> Which U-Boot=20
> version are you using? What DIMM modules are you using? And=20
> what combination=20
> _is_ working?
>=20
> A quick look at the TLB setup shows me, that a maximum of=20
> 512MBytes could be=20
> working. For more at least the TLB setup has to be changed.
>=20
> Best regards,
> Stefan
>=20
> --------------------------------------------------------------
> -----------
> Take Surveys. Earn Cash. Influence the Future of IT
> Join SourceForge.net's Techsay panel and you'll get the=20
> chance to share your
> opinions on IT & business topics through brief surveys -- and=20
> earn cash
> http://www.techsay.com/default.php?page=3Djoin.php&p=3Dsourceforge
&CID=3DDEVDEV
> _______________________________________________
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> U-Boot-Users@...
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>=20

------------------------------------------------------------------------
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I made the change that Marc suggested and still no luck. If both dimms
are in use the system hangs and if only the second Dimm slot is in use I
get:

U-Boot 1.1.4 (Sep 30 2006 - 10:08:43)

CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
MHz)
       I2C boot EEPROM enabled
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  ERROR: Cannot determine a common read delay.
### ERROR ### Please RESET the board ###
=20

Any Ideals?

 Gerald

-----Original Message-----
From: Gerald Jackson=20
Sent: Saturday, September 30, 2006 10:13 AM
To: Marc.Howard@...; sr@...;
u-boot-users@...
Subject: RE: [U-Boot-Users] (no subject)


Here is the error I get if I use the second DIMMS

U-Boot 1.1.4 (Jul 18 2006 - 07:36:20)

CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
MHz)
       I2C boot EEPROM enabled
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  ERROR: Cannot determine a common read delay.
### ERROR ### Please RESET the board ###

Gerald
=20
=20
-----Original Message-----
From: Gerald Jackson=20
Sent: Friday, September 29, 2006 6:16 PM
To: Marc.Howard@...; sr@...;
u-boot-users@...
Subject: Re: [U-Boot-Users] (no subject)

Marc,

After you make that change you can use both dimms slot on the ocotea
board?

What error did you receive before the modification?

if I use only the second dimm slot with 256M it errors. if I use the
first dimm slot it is ok and if I use both dimms slot it error as well.


I am using 1.1.4.

Gerald

-----Original Message-----
From: "Howard, Marc"<Marc.Howard@...>
Sent: 9/28/06 5:06:26 PM
To: "Stefan Roese"<sr@...>,
"u-boot-users@...>
Subject: Re: [U-Boot-Users] (no subject)

Stefan,

Actually > 256MB won't work correctly.  There is a problem in
board/amcc/ocotea/init.S:

tlbtab:
    tlbtab_start
    tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1,
AC_R|AC_W|AC_X|SA_G|SA_I)
    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1,
AC_R|AC_W|SA_G|SA_I)
    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0,
AC_R|AC_W|AC_X )
    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I
)
    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3,
AC_R|AC_W|SA_G|SA_I )
    tlbtab_en

The line:
=20
tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x00000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )

...should be...

tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0,
AC_R|AC_W|AC_X|SA_G|SA_I )
                                                ^
------------------------------------------------^

The way it currently stands virtual addresses 256-512MB are mapped into
the same region as the 1st 256MB of SDRAM.

Marc Howard


> -----Original Message-----
> From: u-boot-users-bounces@...
> [mailto:u-boot-users-bounces@...] On Behalf=20
> Of Stefan Roese
> Sent: Thursday, September 28, 2006 5:48 AM
> To: u-boot-users@...
> Subject: Re: [U-Boot-Users] (no subject)
>=20
> Hi Gerald,
>=20
> On Thursday 28 September 2006 04:03, Gerald Jackson wrote:
> > Does anyone know why u-boot 1.1.4 fails if you use two dimms in the
> > Ocotea Amcc board?
> >
> > I have try two 256 dimm, two 512 dimm, and one 256 dimm in=20
> the second
> > slot ( nothing in the first slot) it all fails.
> >
> > Is this a know problem with the Ocotea board?
>=20
> No. IIRC, we have tested Ocotea with different DIMM modules.=20
> Which U-Boot=20
> version are you using? What DIMM modules are you using? And=20
> what combination=20
> _is_ working?
>=20
> A quick look at the TLB setup shows me, that a maximum of=20
> 512MBytes could be=20
> working. For more at least the TLB setup has to be changed.
>=20
> Best regards,
> Stefan
>=20
> --------------------------------------------------------------
> -----------
> Take Surveys. Earn Cash. Influence the Future of IT
> Join SourceForge.net's Techsay panel and you'll get the=20
> chance to share your
> opinions on IT & business topics through brief surveys -- and=20
> earn cash
> http://www.techsay.com/default.php?page=3Djoin.php&p=3Dsourceforge
&CID=3DDEVDEV
> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users@...
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>=20

------------------------------------------------------------------------
-
Take Surveys. Earn Cash. Influence the Future of IT
Join SourceForge.net's Techsay panel and you'll get the chance to share
your
opinions on IT & business topics through brief surveys -- and earn cash
http://www.techsay.com/default.php?page=3Djoin.php&p=3Dsourceforge&CID=3D=
DEVDE
V
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U-Boot-Users@...
https://lists.sourceforge.net/lists/listinfo/u-boot-users

Hi Gerald,

On Sunday 01 October 2006 05:04, Gerald Jackson wrote:
> I made the change that Marc suggested and still no luck. If both dimms
> are in use the system hangs

Hangs where? Also upon SDRAM initialization?

> and if only the second Dimm slot is in use I 
> get:
>
> U-Boot 1.1.4 (Sep 30 2006 - 10:08:43)
>
> CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=160, OPB=80, EBC=40
> MHz)
>        I2C boot EEPROM enabled
>        Internal PCI arbiter enabled
>        32 kB I-Cache 32 kB D-Cache
> Board: Ocotea - AMCC PPC440GX Evaluation Board
> I2C:   ready
> DRAM:  ERROR: Cannot determine a common read delay.
> ### ERROR ### Please RESET the board ###
>
> Any Ideals?

Ideals? Not really. But I have an idea! ;-)

How did you get the Board? Directly from AMCC? Did it never work at all?

Your PLB frequency seems strange to me (160MHz). Please try to configure your 
Ocotea to use a different setup, for example 533MHz CPU and 133MHz PLB. Here 
is the output from our Ocotea:

U-Boot 1.1.4-g887e2ec9-dirty (Sep  7 2006 - 11:55:16)

CPU:   AMCC PowerPC 440GX Rev. F at 533.333 MHz (PLB=133, OPB=66, EBC=66 MHz)
       I2C boot EEPROM enabled
       Bootstrap Option F - Boot ROM Location I2C (Addr 0x54)
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  256 MB
FLASH:  5 MB
PCI:   Bus Dev VenId DevId Class Int
        00  01  8086  107c  0200  00
In:    serial
Out:   serial
Err:   serial
Net:   ppc_4xx_eth0, ppc_4xx_eth1, ppc_4xx_eth2, ppc_4xx_eth3

Type "run flash_nfs" to mount root filesystem over NFS

Hit any key to stop autoboot:  0
=>   

Best regards,
Stefan

Stefan,

Yes the board works and Pibs works with both Dimms slot in use.
The board came from AMCC and it is the latest board with the 800MHz
440GX chip on it.

The system hangs upon SDRAM initialization, but only with both dimms
slots used.

I didn't even know this problem exist until another company that is
writing a device driver for me told me that the second DIMMS slot
doesn't work on there board. Sure enough it doesn't work on mines
either.

Gerald

-----Original Message-----
From: Stefan Roese [mailto:sr@...
Sent: Sunday, October 01, 2006 5:23 AM
To: u-boot-users@...
Cc: Gerald Jackson; Marc.Howard@...
Subject: Re: [U-Boot-Users] (no subject)

Hi Gerald,

On Sunday 01 October 2006 05:04, Gerald Jackson wrote:
> I made the change that Marc suggested and still no luck. If both dimms
> are in use the system hangs

Hangs where? Also upon SDRAM initialization?

> and if only the second Dimm slot is in use I=20
> get:
>
> U-Boot 1.1.4 (Sep 30 2006 - 10:08:43)
>
> CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
> MHz)
>        I2C boot EEPROM enabled
>        Internal PCI arbiter enabled
>        32 kB I-Cache 32 kB D-Cache
> Board: Ocotea - AMCC PPC440GX Evaluation Board
> I2C:   ready
> DRAM:  ERROR: Cannot determine a common read delay.
> ### ERROR ### Please RESET the board ###
>
> Any Ideals?

Ideals? Not really. But I have an idea! ;-)

How did you get the Board? Directly from AMCC? Did it never work at all?

Your PLB frequency seems strange to me (160MHz). Please try to configure
your=20
Ocotea to use a different setup, for example 533MHz CPU and 133MHz PLB.
Here=20
is the output from our Ocotea:

U-Boot 1.1.4-g887e2ec9-dirty (Sep  7 2006 - 11:55:16)

CPU:   AMCC PowerPC 440GX Rev. F at 533.333 MHz (PLB=3D133, OPB=3D66, =
EBC=3D66
MHz)
       I2C boot EEPROM enabled
       Bootstrap Option F - Boot ROM Location I2C (Addr 0x54)
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  256 MB
FLASH:  5 MB
PCI:   Bus Dev VenId DevId Class Int
        00  01  8086  107c  0200  00
In:    serial
Out:   serial
Err:   serial
Net:   ppc_4xx_eth0, ppc_4xx_eth1, ppc_4xx_eth2, ppc_4xx_eth3

Type "run flash_nfs" to mount root filesystem over NFS

Hit any key to stop autoboot:  0
=3D>  =20

Best regards,
Stefan

Stefan,

I look more into using both dimms issue and I see two interesting
things.

1. With two dimms it never get pass line 1478 - 1500 in spd_sdram.c.  It
loops once then hangs.

2. If I disable this part (ie break) I get the ERROR: Cannot determine a
common read delay. If I comment out the hang()  It returns but it only
calculated 768MB of memory.

Any sugguests?

Gerald

=20
=20

-----Original Message-----
From: Stefan Roese [mailto:sr@...
Sent: Sunday, October 01, 2006 5:23 AM
To: u-boot-users@...
Cc: Gerald Jackson; Marc.Howard@...
Subject: Re: [U-Boot-Users] (no subject)

Hi Gerald,

On Sunday 01 October 2006 05:04, Gerald Jackson wrote:
> I made the change that Marc suggested and still no luck. If both dimms
> are in use the system hangs

Hangs where? Also upon SDRAM initialization?

> and if only the second Dimm slot is in use I=20
> get:
>
> U-Boot 1.1.4 (Sep 30 2006 - 10:08:43)
>
> CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
> MHz)
>        I2C boot EEPROM enabled
>        Internal PCI arbiter enabled
>        32 kB I-Cache 32 kB D-Cache
> Board: Ocotea - AMCC PPC440GX Evaluation Board
> I2C:   ready
> DRAM:  ERROR: Cannot determine a common read delay.
> ### ERROR ### Please RESET the board ###
>
> Any Ideals?

Ideals? Not really. But I have an idea! ;-)

How did you get the Board? Directly from AMCC? Did it never work at all?

Your PLB frequency seems strange to me (160MHz). Please try to configure
your=20
Ocotea to use a different setup, for example 533MHz CPU and 133MHz PLB.
Here=20
is the output from our Ocotea:

U-Boot 1.1.4-g887e2ec9-dirty (Sep  7 2006 - 11:55:16)

CPU:   AMCC PowerPC 440GX Rev. F at 533.333 MHz (PLB=3D133, OPB=3D66, =
EBC=3D66
MHz)
       I2C boot EEPROM enabled
       Bootstrap Option F - Boot ROM Location I2C (Addr 0x54)
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  256 MB
FLASH:  5 MB
PCI:   Bus Dev VenId DevId Class Int
        00  01  8086  107c  0200  00
In:    serial
Out:   serial
Err:   serial
Net:   ppc_4xx_eth0, ppc_4xx_eth1, ppc_4xx_eth2, ppc_4xx_eth3

Type "run flash_nfs" to mount root filesystem over NFS

Hit any key to stop autoboot:  0
=3D>  =20

Best regards,
Stefan

Hi Gerald,

On Sunday 01 October 2006 19:15, Gerald Jackson wrote:
> I look more into using both dimms issue and I see two interesting
> things.
>
> 1. With two dimms it never get pass line 1478 - 1500 in spd_sdram.c.  It
> loops once then hangs.
>
> 2. If I disable this part (ie break) I get the ERROR: Cannot determine a
> common read delay. If I comment out the hang()  It returns but it only
> calculated 768MB of memory.

Only 768MB? Does this mean you are using more than 512MB? As I mentioned 
earlier, this can't work right now. The TLB setup is for a max. of 512MB.

Please try the attached init.S file. It fixes the issue mentioned by Marc 
Howard _and_ adds TLB entries for a max. of 1GB of DDR. It will be checked 
into the official git tree in a few days.

Please let me know if this changes anything.

Best regards,
Stefan

Stefan,

Thank you for the init.S file.  But the problem still persists.

Here is what I get:
U-Boot 1.1.4 (Oct  1 2006 - 02:58:55)

CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
MHz)
       I2C boot EEPROM enabled
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  DIMM slot 0: populated
DIMM slot 1: populated
DIMM slot 0: DDR SDRAM detected
DIMM slot 1: DDR SDRAM detected
DIMM 0 voltage level supported.
Finish program_cfg0
Finish program_cfg1
Finish program_rtr
tr0: 410b401a
Finish program_tr0
Finish program_bxcr Total_Size 805306368     <----  Here is part of the
problem this should return  about a 1Gig of memory but it only returns
805Megs.  =20

If I try only one dimm and move it to either slot it shows the correct
amount but with two dimms the calculation is wrong.

It seems like I am miss about two (or one) banks from the Dimm which I
assume equals 256M.

I am still working on what is causing the wrong amount.

Gerald


=20
=20
=20

-----Original Message-----
From: Stefan Roese [mailto:sr@...
Sent: Sunday, October 01, 2006 2:00 PM
To: u-boot-users@...
Cc: Gerald Jackson
Subject: Re: [U-Boot-Users] (no subject)

Hi Gerald,

On Sunday 01 October 2006 19:15, Gerald Jackson wrote:
> I look more into using both dimms issue and I see two interesting
> things.
>
> 1. With two dimms it never get pass line 1478 - 1500 in spd_sdram.c.
It
> loops once then hangs.
>
> 2. If I disable this part (ie break) I get the ERROR: Cannot determine
a
> common read delay. If I comment out the hang()  It returns but it only
> calculated 768MB of memory.

Only 768MB? Does this mean you are using more than 512MB? As I mentioned

earlier, this can't work right now. The TLB setup is for a max. of
512MB.

Please try the attached init.S file. It fixes the issue mentioned by
Marc=20
Howard _and_ adds TLB entries for a max. of 1GB of DDR. It will be
checked=20
into the official git tree in a few days.

Please let me know if this changes anything.

Best regards,
Stefan

Hi *,

I have problem w/ at91rm9200 board, Intel LXT971A PHY
Ethernet on U-Boot work well, I'm using tftp to get uImage and initrd to 
SDRAM,
tftp 20000000 /tftpboot/img/uImage
tftp 20400000 /tftpboot/img/uRamdisk.2809.5
setenv bootargs root=/dev/ram

U-Boot> printenv
bootdelay=3
baudrate=115200
ethaddr=DE:AD:BE:EF:01:01
ipaddr=192.168.0.111
serverip=192.168.0.223
netmask=255.255.255.0
stdin=serial
stdout=serial
stderr=serial
bootargs=root=/dev/ram init=/bin/sh

I use linux kernel 2.6.17 w/  this patch 
http://maxim.org.za/AT91RM9200/2.6/2.6.17-sam9261-3.patch.gz
But when i got a shell on linux, i try to ping some host on LAN ... 
nothing happend
# mount -t proc proc /proc
# ifconfig eth0 192.168.0.111
eth0: Link now 100-FullDuplex
# ping 192.168.0.223
PING 192.168.0.223 (192.168.0.223): 56 data bytes

# cat /proc/net/arp
IP address       HW type     Flags       HW address            Mask     
Device
192.168.0.223    0x1         0x0         00:00:00:00:00:00     *        eth0

On my host computer:
(#:/home/tmp/kernelsrc/linux-2.6.17)- arp -a
? (192.168.0.111) at <incomplete> on eth0

Some one told me about Linux get_mac_address problem, but i see that 
Linux got MAC( on dmesg)
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (de:ad:be:ef:01:01)
eth0: Intel LXT971A PHY

So, what am i wrong ?

Thanks,
nm.

p/s: I attached my dmesg, linux dot config file in this email.

dmesg :
Uncompressing 
Linux...................................................................................Linux 
version 2.6.17 (root@...) (gcc version 4.0.0 (DENX ELDK 4.0 
4.0.0)) #8 Mon Oct 2 23:35:056CPU: ARM920Tid(wb) [41129200] revision 0 
(ARMv4T)
Machine: Atmel AT91RM9200-DK
Memory policy: ECC disabled, Data cache writeback
Clocks: CPU 179 MHz, master 59 MHz, main 18.432 MHz
CPU0: D VIVT write-back cache
CPU0: I cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
CPU0: D cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
Built 1 zonelists
Kernel command line: root=/dev/ram init=/bin/sh
AT91: 128 gpio irqs in 4 banks
PID hash table entries: 256 (order: 8, 1024 bytes)
Console: colour dummy device 80x30
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory: 32MB = 32MB total
Memory: 28412KB available (2077K code, 459K data, 100K init)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
checking if image is initramfs...it isn't (no cpio magic); looks like an 
initrd
Freeing initrd memory: 1365K
NET: Registered protocol family 16
Generic PHY: Registered new driver
SCSI subsystem initialized
usbcore: registered new driver usbfs
usbcore: registered new driver hub
NET: Registered protocol family 2
IP route cache hash table entries: 256 (order: -2, 1024 bytes)
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 512 (order: -1, 2048 bytes)
TCP: Hash tables configured (established 1024 bind 512)
TCP reno registered
NetWinder Floating Point Emulator V0.97 (double precision)
Installing knfsd (copyright (C) 1996 okir@...).
Initializing Cryptographic API
io scheduler noop registered
io scheduler anticipatory registered (default)
at91_spi: Baud rate set to 5990400
AT91 SPI driver loaded
AT91 Watchdog Timer enabled (5 seconds, nowayout)
at91_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
at91_usart.1: ttyS1 at MMIO 0xfffc4000 (irq = 7) is a AT91_SERIAL
RAMDISK driver initialized: 16 RAM disks of 8192K size 1024 blocksize
LXT970: Registered new driver
LXT971: Registered new driver
eth0: Link now 100-FullDuplex
eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (de:ad:be:ef:01:01)
eth0: Intel LXT971A PHY
netconsole: not configured, aborting
physmap flash device: 200000 at 10000000
at91_dataflash: AT45DB321B detected [spi0] (4325376 bytes)
Creating 3 MTD partitions on "AT45DB321B.spi0":
0x00000000-0x00042000 : "bootloader"
0x00042000-0x0014a000 : "kernel"
0x0014a000-0x00420000 : "filesystem"
at91_cf: irqs det #64, io #0
usbmon: debugfs is not available
at91_ohci at91_ohci: AT91 OHCI
at91_ohci at91_ohci: new USB bus registered, assigned bus number 1
at91_ohci at91_ohci: irq 23, io mem 0x00300000
usb usb1: Product: AT91 OHCI
usb usb1: Manufacturer: Linux 2.6.17 ohci_hcd
usb usb1: SerialNumber: at91
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
Initializing USB Mass Storage driver...
usb 1-1: new full speed USB device using at91_ohci and address 2
usb 1-1: Product: DataTraveler 2.0
usb 1-1: Manufacturer: Kingston
usb 1-1: configuration #1 chosen from 1 choice
usb 1-2: new low speed USB device using at91_ohci and address 3
usb 1-2: device descriptor read/64, error -110
usb 1-2: device descriptor read/64, error -110
usb 1-2: new low speed USB device using at91_ohci and address 4
usb 1-2: device descriptor read/64, error -110
usb 1-2: device descriptor read/64, error -110
usb 1-2: new low speed USB device using at91_ohci and address 5
usb 1-2: device not accepting address 5, error -110
usb 1-2: new low speed USB device using at91_ohci and address 6
usb 1-2: device not accepting address 6, error -110
scsi0 : SCSI emulation for USB Mass Storage devices
usbcore: registered new driver usb-storage
USB Mass Storage support registered.
usbcore: registered new driver libusual
usbcore: registered new driver usbhid
drivers/usb/input/hid-core.c: v2.6:USB HID core driver
udc: at91_udc version 3 May 2006
mice: PS/2 mouse device common for all mice
at91_rtc at91_rtc: rtc intf: sysfs
at91_rtc at91_rtc: rtc intf: proc
at91_rtc at91_rtc: rtc intf: dev (253:0)
at91_rtc at91_rtc: rtc core: registered at91_rtc as rtc0
AT91 Real Time Clock driver.
i2c /dev entries driver
at91_i2c at91_i2c: AT91 i2c bus driver.
MMC: 4 wire bus mode not supported by this driver - using 1 wire
NET: Registered protocol family 26
TCP bic registered
NET: Registered protocol family 1
NET: Registered protocol family 17
RAMDISK: Compressed image found at block 0
VFS: Mounted root (ext2 filesystem).
Freeing init memory: 100K


BusyBox v(null) ((null)) Built-in shell (msh)
Enter 'help' for a list of built-in commands.

There is an error in  the spd_sdram.c file in a loop statement that is =
wrong if you are using two Dimms.
=20
It missing initializing a part of the second dimm.  So if you have a =
1gig of memory it will show up as 768Megs.
=20
I have correct this but need to know on the procedure for sending a =
patch?
=20
 1730                         /*
   1731                          * enable the bank
   1732                          */
   1733                         cr |=3D SDRAM_BXCR_SDBE;
   1734
   1735                         for (i =3D 0; i < num_banks; i++) {
   1736                          if (dimm_num =3D=3D 1)
   1737                          {
   1738                                 =
bank_parms[ctrl_bank_num[dimm_num]+i+1].        bank_size_bytes =3D      =
 (4 * 1024 * 1024) * bank_size_id;
   1739                                 =
bank_parms[ctrl_bank_num[dimm_num]+i+1].        cr =3D cr;
   1740                          }
   1741                          else
   1742                          {
   1743                                 =
bank_parms[ctrl_bank_num[dimm_num]+i].ba        nk_size_bytes =3D (4 * =
1024 * 1024) * bank_size_id;
   1744                                 =
bank_parms[ctrl_bank_num[dimm_num]+i].cr         =3D cr;
   1745                          }

=20
Without the patch it initializing like this:
0 =3D 256M
1 =3D 256M
1=3D 256M
2=3D 256M
=20
Total 768M
=20
With the patch:
0=3D 256M
1=3D256M
2=3D256M
3=3D256M
=20
Total 1024M
=20
=20
Gerald
________________________________

From: u-boot-users-bounces@... on behalf of Gerald =
Jackson
Sent: Sun 10/1/2006 3:17 PM
To: Stefan Roese; u-boot-users@...
Subject: Re: [U-Boot-Users] (no subject)



Stefan,

Thank you for the init.S file.  But the problem still persists.

Here is what I get:
U-Boot 1.1.4 (Oct  1 2006 - 02:58:55)

CPU:   AMCC PowerPC 440GX Rev. F at 800 MHz (PLB=3D160, OPB=3D80, =
EBC=3D40
MHz)
       I2C boot EEPROM enabled
       Internal PCI arbiter enabled
       32 kB I-Cache 32 kB D-Cache
Board: Ocotea - AMCC PPC440GX Evaluation Board
I2C:   ready
DRAM:  DIMM slot 0: populated
DIMM slot 1: populated
DIMM slot 0: DDR SDRAM detected
DIMM slot 1: DDR SDRAM detected
DIMM 0 voltage level supported.
Finish program_cfg0
Finish program_cfg1
Finish program_rtr
tr0: 410b401a
Finish program_tr0
Finish program_bxcr Total_Size 805306368     <----  Here is part of the
problem this should return  about a 1Gig of memory but it only returns
805Megs. =20

If I try only one dimm and move it to either slot it shows the correct
amount but with two dimms the calculation is wrong.

It seems like I am miss about two (or one) banks from the Dimm which I
assume equals 256M.

I am still working on what is causing the wrong amount.

Gerald






-----Original Message-----
From: Stefan Roese [mailto:sr@...]
Sent: Sunday, October 01, 2006 2:00 PM
To: u-boot-users@...
Cc: Gerald Jackson
Subject: Re: [U-Boot-Users] (no subject)

Hi Gerald,

On Sunday 01 October 2006 19:15, Gerald Jackson wrote:
> I look more into using both dimms issue and I see two interesting
> things.
>
> 1. With two dimms it never get pass line 1478 - 1500 in spd_sdram.c.
It
> loops once then hangs.
>
> 2. If I disable this part (ie break) I get the ERROR: Cannot determine
a
> common read delay. If I comment out the hang()  It returns but it only
> calculated 768MB of memory.

Only 768MB? Does this mean you are using more than 512MB? As I mentioned

earlier, this can't work right now. The TLB setup is for a max. of
512MB.

Please try the attached init.S file. It fixes the issue mentioned by
Marc
Howard _and_ adds TLB entries for a max. of 1GB of DDR. It will be
checked
into the official git tree in a few days.

Please let me know if this changes anything.

Best regards,
Stefan

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Hi Gerald,

On Friday 06 October 2006 18:01, Gerald Jackson wrote:
> There is an error in  the spd_sdram.c file in a loop statement that is
> wrong if you are using two Dimms.
>
> It missing initializing a part of the second dimm.  So if you have a 1gig
> of memory it will show up as 768Megs.
>
> I have correct this but need to know on the procedure for sending a patch?

It's hard to see what you really changed, so please take a look at the README 
under "Submitting Patches:" and send a proper patch.

Thanks.

Best regards,
Stefan

Hi Gerald,

On Wednesday 11 October 2006 03:31, Gerald Jackson wrote:
> There is an error in the spd_sdram.c in cpu/ppc4xx/, file in a loop
> statement that is wrong if you are using two Dimms.
>
> It missing initializing a part of the second dimm.  So if you have a
> 1gig of memory it will show up as 768Megs.

<snip>

> --- spd_sdram.OLD	2006-10-10 09:07:34.000000000 -0400
> +++ spd_sdram.c	2006-10-10 09:15:08.000000000 -0400
> @@ -1733,9 +1733,16 @@ unsigned long program_bxcr(unsigned long
>  			cr |= SDRAM_BXCR_SDBE;
>
>  			for (i = 0; i < num_banks; i++) {
> -				bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
> +				if(dimm_num == 1){
> +					bank_parms[ctrl_bank_num[dimm_num]+i+1].bank_size_bytes =
>  					(4 * 1024 * 1024) * bank_size_id;
> +				bank_parms[ctrl_bank_num[dimm_num]+i+1].cr = cr;
> +				{
> +				else
> +				{

Hmmm??? "{ else {"??? You mean "} else {", right?

> +					bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = (4 * 1024 * 1024) * bank_size_id;
> 				bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; 
> +				}
>  			}
>  		}
>  	}

Your patch seems broken to me. Did you create it by hand? Please try again.

And please also take make sure that you don't violate the conding style.

Thanks.

Best regards,
Stefan

In message <OF015105FC.2114DF88-ON6525723E.001A1966-6525723E.001A23E0@...=
.com> you wrote:
>
> Now I wanted to upgrade my busybox-0.65 to busybox-1.1.3
>  So I installed the new busy box and copied the bin sbin and usr=20
> directories  to the filesytem . When i tried to do tftp it is giving=20
> following errors.
...
> kmod: failed to exec /sbin/modprobe -s -k binfmt-4c46, errno =3D 8 (end=
less=20
> loop)

Are you sure you cross-compile the busybox you iunstalled for the
target system?


Note that all this is completely off topic on this  list.


> Notice: The information contained in this e-mail
..


Please omit such stupid trailers when posting to public mailing lists.

> --=3D_alternative 001A235B6525723E_=3D
> Content-Transfer-Encoding: 7bit
> Content-Type: text/html; charset=3D"us-ascii"

And NEVER post HTML here!

Best regards,

Wolfgang Denk

--=20
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@...
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