I have a custom MPC8560 Board that I=92ve been told to get U-Boot =
working on.
I=92ve added in board definition into it and modified the default =
MPC8560ADS
configuration for it.=A0 I have been able to burn it into flash on the =
board,
and step through it.=A0 U-Boot boots up and configures the TLB and then =
jumps
to the proper place in FLASH to continue the load.=A0 But it seems to go =
off
into the middle of nowhere when it comes to the serial_puts command.=A0 =
From
the JTAG and using the memory map that U-Boot compile makes it gets into =
the
serial_puts function and then jumps off into main memory for some =
reason.=A0
It then halts at where the debugger says is an invalid opcode.
Has anyone seen these sorts of problems before?
The board I=92ve been given is very bare.=A0 It has 256 MByte DDR Main =
RAM,=A0 32
MByte Flash (64k sectors), Ethernet on MII, and Serial on SCC1.=A0 =
Nothing
else on it.
This board use to run VxWorks so I took most of the settings used for =
that
and modified U-boot as following (I hope someone can tell me if I did
something wrong)
Made a new directory for the board
Copied the MPC8560ADS board files to the new location
Copied include/configs/MPC8560ADS.h=A0 to a file matching my new board.
Modified the .h file to meet the new board definitions.=A0 Removed the =
SDRAM
on LBC, and the SPD_EEPROM
Modified the DDR as follows:
=A0=A0=A0 #define CFG_SDRAM_SIZE=A0=A0=A0=A0=A0 =
256=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* DDR is 256MB */
=A0=A0=A0 #define CFG_DDR_CS0_BNDS=A0=A0=A0 0x0000000f=A0=A0=A0=A0=A0 /* =
0-256MB */
=A0=A0=A0 #define CFG_DDR_CS0_CONFIG=A0 0x80000102
=A0=A0=A0 #define CFG_DDR_TIMING_1=A0=A0=A0 0x37344321
=A0=A0=A0 #define CFG_DDR_TIMING_2=A0=A0=A0 0x00000800=A0=A0=A0=A0=A0 /* =
P9-45,may need tuning */
=A0=A0=A0 #define CFG_DDR_CONTROL=A0=A0=A0=A0 0xc2000000=A0=A0=A0=A0=A0 =
/* unbuffered,no DYN_PWR */
=A0=A0=A0 #define CFG_DDR_MODE=A0=A0=A0=A0=A0=A0=A0 =
0x00000062=A0=A0=A0=A0=A0 /* DLL,normal,seq,4/2.5 */
=A0=A0=A0 #define CFG_DDR_INTERVAL=A0=A0=A0 0x05100100=A0=A0=A0=A0=A0 /* =
autocharge,no open page
*/
Modified flash section as:
#define CFG_FLASH_BASE=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0xfe000000=A0=A0=A0=A0=A0 /* start of FLASH 32M */
#define CFG_BR0_PRELIM=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0xfe001001=A0=A0=A0=A0=A0 /* port size 16bit */
#define CFG_OR0_PRELIM=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0xfe000797=A0=A0=A0=A0=A0 /* 16MB Flash */
#define CFG_MAX_FLASH_BANKS=A0=A0=A0=A0 =
1=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* number of banks */
#define CFG_MAX_FLASH_SECT=A0=A0=A0=A0=A0 =
512=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 /* sectors per device */
Which match the settings that were used for VxWorks for this area
I left I2C alone even though the board has no I2C=A0 when I tried to =
remove it
u-boot wouldn=92t compile.
I then modified init.S in the board directory so the TLB looks like:
tlb1_entry:
=A0=A0=A0=A0=A0=A0=A0 entry_start
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * Number of TLB0 and TLB1 entries in the =
following table
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long 12
#if (CFG_CCSRBAR_DEFAULT !=3D CFG_CCSRBAR)
=A0=A0=A0 =A0=A0=A0=A0/*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB0=A0=A0=A0=A0=A0=A0=A0=A0 =
4K=A0=A0=A0=A0=A0 Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xff700000=A0=A0 4K=A0=A0=A0=A0=A0 Initial =
CCSRBAR mapping
=A0=A0=A0=A0=A0=A0=A0=A0 *
=A0=A0=A0=A0=A0=A0=A0=A0 * This ends up at a TLB0 Index=3D=3D0 entry, =
and must not collide
=A0=A0=A0=A0=A0=A0=A0=A0 * with other TLB0 Entries.
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 0, 0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), =
0,0,0,0,1,0,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT),
0,0,0,0,0,1,0,1,0,1)
#else
#error("Update the number of table entries in tlb1_entry")
#endif
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB0=A0=A0=A0=A0=A0=A0=A0=A0 16K=A0=A0=A0=A0 =
Cacheable, non-guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xd001_0000=A0 16K=A0=A0=A0=A0 Temporary =
Global data for initialization
=A0=A0=A0=A0=A0=A0=A0=A0 *
=A0=A0=A0=A0=A0=A0=A0=A0 * Use four 4K TLB0 entries.=A0 These entries =
must be cacheable
=A0=A0=A0=A0=A0=A0=A0=A0 * as they provide the bootstrap memory before =
the memory
=A0=A0=A0=A0=A0=A0=A0=A0 * controler and real memory have been =
configured.
=A0=A0=A0=A0=A0=A0=A0=A0 *
=A0=A0=A0=A0=A0=A0=A0=A0 * These entries end up at TLB0 Indicies 0x10, =
0x14, 0x18 and 0x1c,
=A0=A0=A0=A0=A0=A0=A0=A0 * and must not collide with other TLB0 entries.
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 0, 0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,0,0,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 0, 0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 =
* 1024),
=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00,0,0,0,0,0,0=
,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 =
* 1024),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 0, 0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 =
* 1024),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,0,0,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 =
* 1024),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 0, 0, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + =
12 * 1024),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,0,0,0,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + =
12 * 1024),
=A0=A0=A0=A0 =
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A00,0,0,0,0,1,0,1,=
0,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 0:=A0=A0=A0=A0=A0=A0 16M=A0=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xff000000=A0=A0 16M=A0=A0=A0=A0 FLASH
=A0=A0=A0=A0=A0=A0=A0=A0 * Out of reset this entry is only 4K.
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 0, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + =
0x01000000),
0,0,0,1,0,1,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + =
0x01000000),
0,0,0,0,1,1,1,1,1,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 1:=A0=A0=A0=A0=A0=A0 256M=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0x80000000=A0=A0 256M=A0=A0=A0 PCI1 MEM First =
half
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 1, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), =
0,0,0,0,1,0,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE),
0,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 2:=A0=A0=A0=A0=A0=A0 256M=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0x90000000=A0=A0 256M=A0=A0=A0 PCI1 MEM =
Second half
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 2, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + =
0x10000000),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
0,0,0,0,1,0,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + =
0x10000000),
=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 =
=A0=A0=A0=A00,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 3:=A0=A0=A0=A0=A0=A0 16M=A0=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xfe000000=A0=A0 16M=A0=A0=A0=A0 FLASH
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 3, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), =
0,0,0,1,0,1,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), =
0,0,0,0,1,1,1,1,1,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 5:=A0=A0=A0=A0=A0=A0 64M=A0=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xe000_0000=A0 1M=A0=A0=A0=A0=A0 CCSRBAR
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xe200_0000=A0 16M=A0 =A0=A0=A0PCI1 IO
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 5, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), =
0,0,0,0,1,0,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), =
0,0,0,0,0,1,0,1,0,1)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 7:=A0=A0=A0=A0=A0=A0 16K=A0=A0=A0=A0 =
Non-cacheable, guarded
=A0=A0=A0=A0=A0=A0=A0=A0 * 0xf8000000=A0=A0 16K=A0=A0=A0=A0 BCSR =
registers
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 7, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16K)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR), =
0,0,0,0,1,0,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR), =
0,0,0,0,0,1,0,1,0,1)
#if !defined(CONFIG_SPD_EEPROM)
=A0=A0=A0=A0=A0=A0=A0 /*
=A0=A0=A0=A0=A0=A0=A0=A0 * TLB 8:=A0=A0=A0=A0=A0=A0 256M=A0=A0=A0 DDR
=A0=A0=A0=A0=A0=A0=A0=A0 * 0x00000000=A0=A0 64M=A0=A0=A0=A0 DDR System =
memory
=A0=A0=A0=A0=A0=A0=A0=A0 * 0x04000000=A0=A0 64M=A0=A0=A0=A0 DDR System =
memory
=A0=A0=A0=A0=A0=A0=A0=A0 * Without SPD EEPROM configured DDR, this must =
be setup manually.
=A0=A0=A0=A0=A0=A0=A0=A0 * Make sure the TLB count at the top of this =
table is correct.
=A0=A0=A0=A0=A0=A0=A0=A0 * Likely it needs to be increased by two for =
these entries.
=A0=A0=A0=A0=A0=A0=A0=A0 */
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS0(1, 8, 0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), =
0,0,0,0,0,1,1,0)
=A0=A0=A0=A0=A0=A0=A0 .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE),
0,0,0,0,1,1,1,1,1,1)
#endif
=A0=A0=A0=A0=A0=A0=A0 entry_end
Modified the Local Address window to:
#if !defined(CONFIG_SPD_EEPROM)
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
/*#define LAWAR0=A0=A0=A0=A0=A0=A0=A0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | =
(LAWAR_SIZE &
LAWAR_SIZE_256M))*/
#define LAWAR0 0x80f0001b
#else
#define LAWBAR0 0
#define LAWAR0=A0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) =
&
~LAWAR_EN)
#endif
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
#define LAWAR1=A0 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE &
LAWAR_SIZE_512M))
/*
=A0* This is not so much the FLASH map as it is the whole localbus map.
=A0*/
#define LAWBAR2 ((CFG_FLASH_BASE>>12) & 0xfffff)
#define LAWAR2=A0 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE &
LAWAR_SIZE_32M))
law_entry:
=A0=A0=A0=A0=A0=A0=A0 entry_start
=A0=A0=A0=A0=A0=A0=A0 .long 0x04
=A0=A0=A0=A0=A0=A0=A0 .long =
LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
=A0=A0=A0=A0=A0=A0=A0 entry_end
Anyone have any idea on what I=92ve done wrong?=A0 Are there any other =
board
definitions in U-Boot I could use that might meet what I have better?
Peter Wright
Senior Software Engineer
Base Station Development
CDMA Division
Main: 1-604-276-0055
Direct: 1-604-303-8599=A0 ext 267
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