On Thursday 25 January 2007 08:50, george john wrote:
> > EECON2 = 0x55; // Write "password" to EECON2
> > EECON2 = 0xAA;
> > WR = 1; // Initiate a write cycle
> >
Well, the PIC Datasheet claims that an exact timed sequence is neccessary to
write the internal eeprom:
[quote the datasheet:]
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
[/quote]
Depending on the compiler optimization, redundand banksels etc, your EECON2
writes won't be translated into the exact reqired ASM sequence.
Please check the intermediate ASM code generated by SDCC if that is the case.
The only solution working regardless of compiler version and settings would be
to implement it in inline ASM, like
[quote datasheet:]
BSF STATUS,RP0 ;Bank 1
BSF EECON1,WREN ;Enable write
BCF INTCON,GIE ;Disable INTs
MOVLW 55h ;Unlock write
MOVWF EECON2 ;
MOVLW AAh ;
MOVWF EECON2 ;
BSF EECON1,WR ;Start the write
BSF INTCON,GIE ;Enable INTS
[/quote]
HTH,
/Ernst
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