> digging through cedet-devel email archive, I found the conversation
> between Andy Pfeiffer and Andrea Fedeli in Nov 2012. It seems that
> Andrea has started writing wisent parser for SystemVerilog.
Yes, I wrote a dumb complete [?] Wisent SystemVerilog grammar, back in
March 2011. V0.0
At the time I sent that two *really* skilled people in the field, to
let them use it as a possible starting point, but, as far as I can
tell, nothing came out of that, surely a not too good sign about my
grammar quality :/
In November 2012 I did the further sent, to Andy, in its 0.0 version
(still the current one, at least on my side :) ). In spite of my
hopes, I had no good time to do anything on it.
I finally found the time, yesterday, to play with it again a little
bit; at least getting the CEDET trunk version re-digesting it. As far
as I can recall, Wisent diagnostics received a significant
> I am interested in cedet support of SystemVerilog.
> Can I get a hold of the work that has been done so far, so that I can
> use it and also help develop it?
I've just started a project on Sourceforge, it goes under the name
I'm a sourceforge rookie from project management point of view, but
following the reported suggestion I suceeded in uploading the sources
Let's see whether we can get something useful out of that.