On 1/19/06, George Francis <chaostoo@...> wrote:
> > I'm running i2c at 100 kHz right now. In theory it can do 400 kHz.
> > I'll probably test that once the i2c boot loader is delivered.
> I've not managed to get the I2C to run at 400KHz. You can set one of
> the pxa registers with pxaregs, now the clock pin toggles at 400KHz,
> but there are big gaps between the bytes.
That's actually expected. The way i2c works is that the master sets
the clock speed, but the slave is allowed to stretch it, typically
during the ACK byte.
The clock line is open collector, so the master drives it low, and the
slave can also choose to drive it low. The master releases the clock
and has to observe it rise before trying to clock out the next bit.
> Measuring it on a scope
> shows data transfer at about 230KBPS (averaged over a few bytes). I
> suspect there may be options that need changing on the kernel driver
> to make it run at 400K.
Vancouver, BC, Canada