I think I've got it now, do correct me if I'm wrong, table 11-2
GPMC Pin Multiplexing Options helped clarify things for me.
The design for the GPMC aims at minimizing the number of pins required
to interface with an external memory/device. So, they've multiplexed
it. If I don't use multiplexing, I'll be limited to a 2 Kbyte
addressing space a[10:1].
If I use the multiplexing option, I'll have a 16-bit addressing space,
and for a 16-bit device, only address lines a[26:11] will be used to
get 16-bit addressing, and address lines a[10:1] will not be used.
Does this mean that if, for some reason, need to utilize all 26 lines,
the system will allow me to address at 24-bits?
On Feb 26, 2009, at 12:02 PM, Elvis Dowson wrote:
> Hi Murphy,
> I'm trying to interface the OMAP GPMC to a Xilinx Virtex-5 FPGA.
> Now there are two modes that are described in page 1180 and 1181 of
> the OMAP 35xx technical reference manual (rev. B).
> GPMC to 16-Bit Address/Data-Multiplexed Memory
> GPMC to 16-Bit NAND Device
> Question 01: What is confusing for me is the fact that they refer to
> the GPMC as being 16-bit wide for address and 16-bit wide for data,
> but when I look at the diagram for GPMC to 16-Bit Address/Data-
> Multiplexed Memory, it shown that you have 26-bits for the address
> and 16-bits for the data, when you use the multiplexed mode.
> Question 02: When using it in GPMC to 16-Bit NAND Device
> configuration, it appears that the address and data lines are
> multiplexed anyway, i.e A[16:1]/D[15:0] = gpmc_d[15:0]
> All very confusing!! :-)
> Question 03: Which mode would you recommend I use to interface it
> with the Xilinx Virtex-5 FPGA, i.e. the simplest approach?
> Best regards,
> On Feb 25, 2009, at 10:04 PM, R. P. McMurphy wrote:
>> physically A1-A26 on the pins for 128MB address space.per chip