I guess you're chinese and the language barrier is hindering you to
clearly write down what you mean. But please try to be a bit more
specific. What I understand now is that you have access to the STC
51 core design and that your company (lab) has modified its pipeline
and external code memory interface. For the latter you also added
extra instructions and registers.
Have you sacrificed/modified any original 51 instructions to
accomodate this or have you used the only unused opcode 0xA5 to
And are those extra registers in the SFR area or do they need the
Is the stack handling unmodified? (e.g. LCALL/RET)
Most companies extend the 51 architecture through the SFR's for
compatibility reasons. For example to use 128kB flash they support
bank switching selecting the bank through an SFR.
> my lab has modify the STC 51 architecture. Generally have the following two aspects:
> 1.The original six pipeline instead of two pipeline.Aiming at accelerate the 8051 processing
> The first machine cycle, read the instruction and functional decode;
> The two machine cycle,operating instructions and write data to relevant registers
> 2.Increase an extern flash chip,to expand the ROM spatial capacity
> In order to coordinate the amendment,we have added a few instructions to control the flash, at the same time, we have added some new registers to latch the operation codes of flash
> Basically only these!
> So,what should I do?