Norbert Egi wrote:
> John Sigler wrote:
>> opcontrol "tells" the CPU you are interested in cache misses,
>> i.e. it configures the CPU to increment a counter every time
>> a cache miss occurs. When that hardware counter reaches the
>> value you specified (100,000 in your case) an interrupt is
>> generated, and the interrupt handler can sample the instruction
>> pointer (aka program counter).
>> Statistically, instructions that generate more cache misses will
>> be sampled more often.
> Ah, ok, so not the counter, that counts the specified event, is
> sampled, but the program counters are sampled after every (in my
> case) 100.000th event.
I'm not sure why you write "program counters" (plural).
The so-called "program counter" (IMO, the term "instruction pointer"
is more descriptive) is a hardware register which holds the address
(in virtual memory) of the current (or of the next) instruction.
> So, if I want to get the approximated total number of cache misses I
> simply multiply the results oprofile presents by the specified count
> (100.000 now)? So the CPU frequency doesn't matter at all in this
As far as my understanding of profiling goes, yes to both.
(Someone please correct me if I've made incorrect statements.)