CEDET

Hello,

Has anyone done any work on CEDET support for SystemVerilog?

I saw some postings from a couple of years ago, but I'm not sure if
anything came of it.

If so, could you send me the code so I could help out with support?

 

Thanks,

Andy Pfeiffer

Re: [CEDET-devel] SystemVerilog Support From: Andrea Fedeli <andrea.fedeli@mc...> - 2012-11-13 07:53 Attachments: wisent-sverilog.wy.pdf      John.Pfeiffer@... wrote: > > Hello, > > Has anyone done any work on CEDET support for SystemVerilog? > > I saw some postings from a couple of years ago, but I’m not sure if anything came of it. > > If so, could you send me the code so I could help out with support? > Hi John! I did a trial beginning 2011, I tagged it 0.0 for a sensible reason ;) ; my attempt was an almost direct derivation of the 2005 IEEE 1800 SystemVerilog Standard Annex A [Formal Syntax], with the strictly needed LALR rewriting, and a few other "embellishments", to get a source for wisent. It flourished into about a thousand conflicts, as far as I remember; if you like I can share that with you. It contains 382 terminals, 1063 nonterminals and 3402 production rules. I've just checked, and seen I sent it to Wilson Snyder, one of the two maintainers of the amazing Verilog mode (and author of the auto extensions, AFAIK), in March 2011; as far as I can tell it didn't go into anything, hence I'm afraid it won't be of much aid for us either. I used it with the CEDET 1.0, and I did not update it any further. BTW, it would make sense to update the grammar to the 2009 version (I got that afterward). Please find attached the grammar graph (an arc goes from A to B if a production rule with LHS A has B in the RHS); please write me if you want to have a crack at it. Cheers, Andrea.

Re: [CEDET-devel] SystemVerilog Support From: Andrea Fedeli <andrea.fedeli@mc...> - 2012-11-13 14:52 John.Pfeiffer@... wrote: > > Hello, > > Has anyone done any work on CEDET support for SystemVerilog? > > I saw some postings from a couple of years ago, but I’m not sure if anything came of it. > > If so, could you send me the code so I could help out with support? > Hi John! I did a trial beginning 2011, I tagged it 0.0 for a sensible reason ;) ; my attempt was an almost direct derivation of the 2005 IEEE 1800 SystemVerilog Standard Annex A [Formal Syntax], with the strictly needed LALR rewriting, and a few other "embellishments", to get a source for wisent. It flourished into about a thousand conflicts, as far as I remember; if you like I can share that with you. It contains 382 terminals, 1063 nonterminals and 3402 production rules. I've just checked, and seen I sent it to Wilson Snyder, one of the two maintainers of the amazing Verilog mode (and author of the auto extensions, AFAIK), in March 2011; as far as I can tell it didn't go into anything, hence I'm afraid it won't be of much aid for us either. I used it with CEDET 1.0, and I did not update it any further. BTW, it would make sense to update the grammar to the 2009 version (I got that afterward). If all this sounds of any interest to you I can start sending you the the grammar graph and the wisent file I wrote at the time. Cheers, Andrea.

Re: [CEDET-devel] SystemVerilog Support From: <John.Pfeiffer@L-...> - 2012-11-13 19:34 Hi Andrea, That sounds great, send it on along. I tried diving in myself with a very simple grammar and parser on a small example file last week and couldn't get it all to work. It will be nice to have some existing files to go off of. Thanks, Andy Pfeiffer -----Original Message----- From: Andrea Fedeli [mailto:andrea.fedeli@...] Sent: Tuesday, November 13, 2012 9:52 AM To: Pfeiffer, John @ SSG - ISS - CIN Cc: cedet-devel@... Subject: Re: [CEDET-devel] SystemVerilog Support John.Pfeiffer@... wrote: > > Hello, > > Has anyone done any work on CEDET support for SystemVerilog? > > I saw some postings from a couple of years ago, but I'm not sure if anything came of it. > > If so, could you send me the code so I could help out with support? > Hi John! I did a trial beginning 2011, I tagged it 0.0 for a sensible reason ;) ; my attempt was an almost direct derivation of the 2005 IEEE 1800 SystemVerilog Standard Annex A [Formal Syntax], with the strictly needed LALR rewriting, and a few other "embellishments", to get a source for wisent. It flourished into about a thousand conflicts, as far as I remember; if you like I can share that with you. It contains 382 terminals, 1063 nonterminals and 3402 production rules. I've just checked, and seen I sent it to Wilson Snyder, one of the two maintainers of the amazing Verilog mode (and author of the auto extensions, AFAIK), in March 2011; as far as I can tell it didn't go into anything, hence I'm afraid it won't be of much aid for us either. I used it with CEDET 1.0, and I did not update it any further. BTW, it would make sense to update the grammar to the 2009 version (I got that afterward). If all this sounds of any interest to you I can start sending you the the grammar graph and the wisent file I wrote at the time. Cheers, Andrea.

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