Below are patches that add MIPS support for the performance counters in
the MIPS R10000, R12000, QED RM7000, PMC-Sierra RM9000, Sibyte SB1,
NEC VR5432, VR5500, VR5532 and VR7701 to the userspace part of oprofile.
Please merge, thanks.
Ralf
ChangeLog | 27 +++++
README | 2
daemon/opd_cookie.c | 11 ++
events/Makefile.am | 11 +-
events/Makefile.in | 9 +
events/mips/r10000/events | 36 +++++++
events/mips/r10000/unit_masks | 5 +
events/mips/r12000/events | 35 +++++++
events/mips/r12000/unit_masks | 7 +
events/mips/rm7000/events | 34 +++++++
events/mips/rm7000/unit_masks | 5 +
events/mips/rm9000/events | 32 +++++++
events/mips/rm9000/unit_masks | 5 +
events/mips/sb1/events | 73 +++++++++++++++
events/mips/sb1/unit_masks | 5 +
events/mips/vr5432/events | 14 +++
events/mips/vr5432/unit_masks | 5 +
events/mips/vr5500/events | 16 +++
events/mips/vr5500/unit_masks | 5 +
libop/op_cpu_type.c | 7 +
libop/op_cpu_type.h | 7 +
libop/op_events.c | 19 ++++
23 files changed, 367 insertions(+), 195 deletions(-)
diff -purN oprofile-0.8.1.orig/ChangeLog oprofile-0.8.1/ChangeLog
--- oprofile-0.8.1.orig/ChangeLog Sat Sep 11 20:33:26 2004
+++ oprofile-0.8.1/ChangeLog Sun Dec 12 16:58:49 2004
@@ -1,3 +1,30 @@
+2004-12-12 Ralf Baechle <ralf@...>
+
+ * daemon/opd_cookie.c: Define __NR_lookup_dcookie for all three ABIs
+ supported ABIs.
+ * events/mips/r10000/events: New file
+ * events/mips/r10000/unit_masks: New file
+ * events/mips/r12000/events: New file
+ * events/mips/r12000/unit_masks: New file
+ * events/mips/r5432/events: New file
+ * events/mips/r5432/unit_masks: New file
+ * events/mips/r5500/events: New file
+ * events/mips/r5500/unit_masks: New file
+ * events/mips/rm7000/events: New file
+ * events/mips/rm7000/unit_masks: New file
+ * events/mips/rm9000/events: New file
+ * events/mips/rm9000/unit_masks: New file
+ * events/mips/sb1/events: New file
+ * events/mips/sb1/unit_masks: New file
+ * events/Makefile.am: List new files for MIPS in event_files.
+ * events/Makefile.in: Rebuild.
+ * events/Makefile: Likewise.
+ * libop/op_cpu_type.c: Add entries for the MIPS R10000 and R12000,
+ QED RM7000 and PMC-Sierra RM9000, NEC VR5432 and VR5500 and Sibyte SB1
+ processors.
+ * libop/op_cpu_type.h: Add entries for the same processors to op_cpu.
+ * README: List myself as the caretaker of the MIPS bits.
+
2004-09-11 John Levon <levon@...>
* configure.in: bump to 0.8.1
diff -purN oprofile-0.8.1.orig/README oprofile-0.8.1/README
--- oprofile-0.8.1.orig/README Mon Sep 15 03:20:30 2003
+++ oprofile-0.8.1/README Sun Dec 12 16:58:21 2004
@@ -19,6 +19,8 @@ oprofile release, and contributed bug fi
Graydon Hoare <graydon@...> provided P4 port, bug fixes and cleanups.
+Ralf Baechle <ralf@...> provided the MIPS port.
+
Other contributors are listed in the ChangeLog.
Building
diff -purN oprofile-0.8.1.orig/daemon/opd_cookie.c oprofile-0.8.1/daemon/opd_cookie.c
--- oprofile-0.8.1.orig/daemon/opd_cookie.c Sat May 29 19:02:59 2004
+++ oprofile-0.8.1/daemon/opd_cookie.c Fri Dec 10 14:48:08 2004
@@ -40,6 +40,17 @@
#define __NR_lookup_dcookie 110
#elif defined(__arm__)
#define __NR_lookup_dcookie (__NR_SYSCALL_BASE+249)
+#elif defined(__mips__)
+#include <sgidefs.h>
+#if _MIPS_SIM == _MIPS_SIM_ABI32
+#define __NR_lookup_dcookie 4247 /* O32 */
+#elif _MIPS_SIM == _MIPS_SIM_ABI64
+#define __NR_lookup_dcookie 5206 /* N64 */
+#elif _MIPS_SIM == _MIPS_SIM_NABI32
+#define __NR_lookup_dcookie 6206 /* N32 */
+#else
+#error Unknown MIPS ABI: Dunno __NR_lookup_dcookie
+#endif
#else
#error Please define __NR_lookup_dcookie for your architecture
#endif
diff -purN oprofile-0.8.1.orig/events/Makefile.am oprofile-0.8.1/events/Makefile.am
--- oprofile-0.8.1.orig/events/Makefile.am Wed Apr 7 17:01:03 2004
+++ oprofile-0.8.1/events/Makefile.am Sun Dec 12 22:21:07 2004
@@ -1,4 +1,4 @@
-event_files = \
+Event_files = \
alpha/ev4/events alpha/ev4/unit_masks \
alpha/ev5/events alpha/ev5/unit_masks \
alpha/ev67/events alpha/ev67/unit_masks \
@@ -17,7 +17,14 @@ event_files = \
rtc/events rtc/unit_masks \
x86-64/hammer/events x86-64/hammer/unit_masks \
arm/xscale1/events arm/xscale1/unit_masks \
- arm/xscale2/events arm/xscale2/unit_masks
+ arm/xscale2/events arm/xscale2/unit_masks \
+ mips/rm7000/events mips/rm7000/unit_masks \
+ mips/rm9000/events mips/rm9000/unit_masks \
+ mips/sb1/events mips/sb1/unit_masks \
+ mips/r10000/events mips/r10000/unit_masks \
+ mips/r12000/events mips/r12000/unit_masks \
+ mips/vr5432/events mips/vr5432/unit_masks \
+ mips/vr5500/events mips/vr5500/unit_masks
install-data-local:
for i in ${event_files} ; do \
diff -purN oprofile-0.8.1.orig/events/Makefile.in oprofile-0.8.1/events/Makefile.in
--- oprofile-0.8.1.orig/events/Makefile.in Sat Sep 11 19:45:43 2004
+++ oprofile-0.8.1/events/Makefile.in Sun Dec 12 22:21:17 2004
@@ -131,7 +131,14 @@ event_files = \
rtc/events rtc/unit_masks \
x86-64/hammer/events x86-64/hammer/unit_masks \
arm/xscale1/events arm/xscale1/unit_masks \
- arm/xscale2/events arm/xscale2/unit_masks
+ arm/xscale2/events arm/xscale2/unit_masks \
+ mips/rm7000/events mips/rm7000/unit_masks \
+ mips/rm9000/events mips/rm9000/unit_masks \
+ mips/sb1/events mips/sb1/unit_masks \
+ mips/r10000/events mips/r10000/unit_masks \
+ mips/r12000/events mips/r12000/unit_masks \
+ mips/vr5432/events mips/vr5432/unit_masks \
+ mips/vr5500/events mips/vr5500/unit_masks
EXTRA_DIST = $(event_files)
diff -purN oprofile-0.8.1.orig/events/mips/r10000/events oprofile-0.8.1/events/mips/r10000/events
--- oprofile-0.8.1.orig/events/mips/r10000/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/r10000/events Sun Dec 12 14:46:30 2004
@@ -0,0 +1,36 @@
+#
+# R10000 events
+#
+# The same event numbers mean different things on the two counters
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
+event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
+event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
+event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
+event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
+event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
+event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
+event:0x05 counters:0 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:0x05 counters:1 um:zero minimum:500 name:FP_INSTRUCTON_GRADUATED : Floating-point instructions graduated
+event:0x06 counters:0 um:zero minimum:500 name:BRANCHES_RESOLVED : Branches resolved
+event:0x06 counters:1 um:zero minimum:500 name:QUADWORDS_WB_FROM_PRIMARY_DCACHE : Quadwords written back from primary data cache
+event:0x07 counters:0 um:zero minimum:500 name:QUADWORDS_WB_FROM_SCACHE : Quadwords written back from secondary cache
+event:0x07 counters:1 um:zero minimum:500 name:TLB_REFILL_EXCEPTIONS : TLB refill exceptions
+event:0x08 counters:0 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS_SCACHE : Correctable ECC errors on secondary cache data
+event:0x08 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
+event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x09 counters:1 um:zero minimum:500 name:SCACHE_LOAD_STORE_CACHEOP_OPERATIONS : Secondary cache load / store and cache-ops operations
+event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
+event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
+event:0x0b counters:0 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_INSN : Secondary cache way mispredicted (instruction)
+event:0x0b counters:1 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_DATA : Secondary cache way mispredicted (data)
+event:0x0c counters:0 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ : External intervention requests
+event:0x0c counters:1 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ_HITS_SCACHE : External intervention request is determined to have hit in secondary cache
+event:0x0d counters:0 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ : External invalidate requests
+event:0x0d counters:1 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ_HITS_SCACHE : External invalidate request is determined to have hit in secondary cache
+event:0x0e counters:0 um:zero minimum:500 name:FUNCTIONAL_UNIT_COMPLETION_CYCLES : Functional unit completion cycles
+event:0x0e counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with store hint to CleanExclusive secondary cache blocks
+event:0x0f counters:0 um:zero minimum:500 name:INSTRUCTION_GRADUATED : Instructions graduated
+event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores or prefetches with store hint to Shared secondary cache blocks
diff -purN oprofile-0.8.1.orig/events/mips/r10000/unit_masks oprofile-0.8.1/events/mips/r10000/unit_masks
--- oprofile-0.8.1.orig/events/mips/r10000/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/r10000/unit_masks Sun Dec 12 22:16:40 2004
@@ -0,0 +1,5 @@
+#
+# MIPS R10000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/r12000/events oprofile-0.8.1/events/mips/r12000/events
--- oprofile-0.8.1.orig/events/mips/r12000/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/r12000/events Sun Dec 12 22:15:47 2004
@@ -0,0 +1,35 @@
+#
+# R12000 events
+#
+event:0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
+event:1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
+event:2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
+event:3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
+event:4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
+event:5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
+event:7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
+event:8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
+event:9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:10 counters:0,1,2,3 um:zero minimum:500 nameINSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
+event:11 counters:0,1,2,3 um:zero minimum:500 name:SECONDARY_CACHE_WAY_MISSPREDICTED : Secondary cache way mispredicted (instruction)
+event:12 counters:0,1,2,3 um:zero minimum:500 name:INTERVENTION_REQUESTS : External intervention requests
+event:13 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_REQUESTS : External invalidate requests
+
+event:15 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:16 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_INSTRUCTIONS_EXECUTED : Executed prefetch instructions
+event:17 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
+event:18 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_LOADS : Graduated loads
+event:19 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORES : Graduated stores
+event:20 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORE_CONDITIONALS : Graduated store conditionals
+event:21 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_FP_INSTRUCTIONS : Graduated floating point instructions
+event:22 counters:0,1,2,3 um:zero minimum:500 name:QUADWORDS : Quadwords written back from primary data cache
+event:23 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
+event:24 counters:0,1,2,3 um:zero minimum:500 name:MISPREDICTED_BRANCHES : Mispredicted branches
+event:25 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
+event:26 counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
+event:27 counters:0,1,2,3 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTION : Misprediction from scache way prediction table (data)
+event:28 counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_SCACHE_INTERVENTION_HIT : State of external intervention hit in secondary cache
+event:29 counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_EXTERNAL_INVALIDATION_HIT : State of external invalidation hits in secondary cache
+event:30 counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_TO_CLEAN_SC_BLOCK : Store/prefetch exclusive to clean block in secondary cache
+event:31 counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_SHARED_SC_BLOCK : Store/prefetch exclusive to shared block in secondary
diff -purN oprofile-0.8.1.orig/events/mips/r12000/unit_masks oprofile-0.8.1/events/mips/r12000/unit_masks
--- oprofile-0.8.1.orig/events/mips/r12000/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/r12000/unit_masks Sun Dec 12 22:16:43 2004
@@ -0,0 +1,7 @@
+#
+# MIPS R12000 possible unit masks
+#
+# We don't support the R12000 conditional count feature yet.
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/rm7000/events oprofile-0.8.1/events/mips/rm7000/events
--- oprofile-0.8.1.orig/events/mips/rm7000/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/rm7000/events Sun Dec 12 14:21:33 2004
@@ -0,0 +1,34 @@
+#
+# RM7000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
+event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branches issued
+event:0x13 counters:0,1 um:zero minimum:500 name:SCACHE_WRITEBACKS : Secondary cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:PCACHE_WRITEBACKS : Primary cache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
+event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
+event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles
+event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles
+event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non-blocking loads - stall start of exception
diff -purN oprofile-0.8.1.orig/events/mips/rm7000/unit_masks oprofile-0.8.1/events/mips/rm7000/unit_masks
--- oprofile-0.8.1.orig/events/mips/rm7000/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/rm7000/unit_masks Sun Dec 12 22:17:03 2004
@@ -0,0 +1,5 @@
+#
+# MIPS RM7000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/rm9000/events oprofile-0.8.1/events/mips/rm9000/events
--- oprofile-0.8.1.orig/events/mips/rm9000/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/rm9000/events Sun Dec 12 22:02:58 2004
@@ -0,0 +1,32 @@
+#
+# RM9000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branch instructions issued
+event:0x13 counters:0,1 um:zero minimum:500 name:L2_WRITEBACKS : L2 cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Dcache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_REMISSES : Cache remisses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
+event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
+event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
+event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non-blocking loads - stall start of exception
diff -purN oprofile-0.8.1.orig/events/mips/rm9000/unit_masks oprofile-0.8.1/events/mips/rm9000/unit_masks
--- oprofile-0.8.1.orig/events/mips/rm9000/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/rm9000/unit_masks Fri Dec 10 01:50:51 2004
@@ -0,0 +1,5 @@
+#
+# MIPS RM9000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/sb1/events oprofile-0.8.1/events/mips/sb1/events
--- oprofile-0.8.1.orig/events/mips/sb1/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/sb1/events Sun Dec 12 22:18:28 2004
@@ -0,0 +1,73 @@
+#
+# Sibyte SB1 events
+#
+
+event:16 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
+
+# Execution Counts and Instruction Slotting
+event:40 counters:1,2,3 um:zero minimum:500 name:ISSUE_L0 :Issue to L0
+event:41 counters:1,2,3 um:zero minimum:500 name:ISSUE_L1 :Issue to L0
+event:42 counters:1,2,3 um:zero minimum:500 name:ISSUE_E0 :Issue to E0
+event:43 counters:1,2,3 um:zero minimum:500 name:ISSUE_E1 :Issue to E1
+
+# Explaining Sub-Peak Performance: Pipeline Traps
+event:47 counters:1,2,3 um:zero minimum:500 name:BRANCH_MISSPREDICTS :Branch mispredicts
+event:29 counters:0,1,2,3 um:zero minimum:500 name:MBOX_REPLAY :MBOX replay
+event:28 counters:0,1,2,3 um:zero minimum:500 name:DCFIFO :DCFIFO
+event:30 counters:0,1,2,3 um:zero minimum:500 name:DATA_DEPENDENCY_REPLAY :Data dependency replay
+event:27 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_FILL_REPLAY :Dcache fill replay
+event:31 counters:0,1,2,3 um:zero minimum:500 name:ANY_REPLAY :Any replay except mispredict
+
+
+# Explaining Sub-Peak Performance: static and dynamic stalls
+event:32 counters:1,2,3 um:zero minimum:500 name:MAX_ISSUE :Max issue
+event:33 counters:1,2,3 um:zero minimum:500 name:NO_VALID_INSN :No valid instr to issue
+event:34 counters:1,2,3 um:zero minimum:500 name:CONSUMER_WAITING_FOR_LOAD :load consumer waiting for dfill
+event:35 counters:1,2,3 um:zero minimum:500 name:NOT_DATA_READY :Not data ready
+event:36 counters:1,2,3 um:zero minimum:500 name:RESOURCE_CONSTRAINT :Resource (L0/1 E0/1) constraint
+event:37 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_IMISS :issue conflict due to imiss using LS0
+event:38 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_DFILL :issue conflict due to dfill using LS0/1
+
+# Grouping Co-issued Instructions
+event:39 counters:1,2,3 um:zero minimum:500 name:INSN_STAGE4 :One or more instructions survives stage 4
+
+# Branch information
+event:44 counters:1,2,3 um:zero minimum:500 name:BRANCH_STAGE4 :Branch survived stage 4
+event:45 counters:1,2,3 um:zero minimum:500 name:BRANCH_REALLY_TAKEN :Conditional branch was really taken
+event:46 counters:1,2,3 um:zero minimum:500 name:BRANCH_PREDICTED_TAKEN :Predicted taken conditional branch
+
+# Cache access
+event:1 counters:1,2,3 um:zero minimum:500 name:RQ_LENGTH :Read queue length
+event:2 counters:1,2,3 um:zero minimum:500 name:UNCACHED_RQ_LENGTH :Number of valid uncached entries in read queue
+event:3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+
+event:10 counters:1,2,3 um:zero minimum:500 name:DCACHE_FILLED_SHD_NONC_EXC :Dcache is filled (shared, nonc, exclusive)
+event:11 counters:1,2,3 um:zero minimum:500 name:DCACHE_FILL_SHARED_LINE :Dcache is filled with shared line
+event:12 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+event:15 counters:1,2,3 um:zero minimum:500 name:WRITEBACK_RETURNS :Number of instruction returns
+event:13 counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to replacement
+event:7 counters:1,2,3 um:zero minimum:500 name:UPGRADE_SHARED_TO_EXCLUSIVE :A line is upgraded from shared to exclusive
+event:6 counters:1,2,3 um:zero minimum:500 name:LD_ST_HITS_PREFETCH_IN_QUEUE :Load/store hits prefetch in read queue
+event:5 counters:1,2,3 um:zero minimum:500 name:PREFETCH_HITS_CACHE_OR_READ_Q :Prefetch hits in cache or read queue
+event:4 counters:1,2,3 um:zero minimum:500 name:READ_HITS_READ_Q :Read hits in read queue
+
+# BIU
+
+event:17 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_ADDR_BUS :BIU stalls on ZB addr bus
+event:18 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_DATA_BUS :BIU stalls on ZB data bus
+event:19 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Requests sent to ZB Abus
+event:20 counters:1,2,3 um:zero minimum:500 name:READ_RQ_NOPS_SENT_TO_ABUS :Read requests and NOPs sent to ZB Abus
+event:21 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Read requests sent to ZB Abus
+event:14 counters:1,2,3 um:zero minimum:500 name:MBOX_RQ_WHEN_BIU_BUSY :MBOX requests to BIU when BIU busy
+
+# Multiprocessor
+event:26 counters:1,2,3 um:zero minimum:500 name:STORE_COND_FAILED :Failed store conditional
+event:22 counters:1,2,3 um:zero minimum:500 name:SNOOP_RQ_HITS :Snoop request hits anywhere
+event:23 counters:1,2,3 um:zero minimum:500 name:SNOOP_ADDR_Q_FULL :Snoop address queue is full
+event:24 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE :Read response comes from the other core
+event:25 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE_D_MOD :Read response comes from the other core with D_MOD set
+
+# Instruction Counts
+event:8 counters:1,2,3 um:zero minimum:500 name:LOAD_SURVIVED_STAGE4 :Load survived stage 4
+event:9 counters:1,2,3 um:zero minimum:500 name:STORE_SURVIVED_STAGE4 :Store survived stage 4
+event:0 counters:1,2,3 um:zero minimum:500 name:INSN_SURVIVED_STAGE7 :Instruction survived stage 7
diff -purN oprofile-0.8.1.orig/events/mips/sb1/unit_masks oprofile-0.8.1/events/mips/sb1/unit_masks
--- oprofile-0.8.1.orig/events/mips/sb1/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/sb1/unit_masks Sun Dec 12 22:18:49 2004
@@ -0,0 +1,5 @@
+#
+# Sibyte SB1 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/vr5432/events oprofile-0.8.1/events/mips/vr5432/events
--- oprofile-0.8.1.orig/events/mips/vr5432/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/vr5432/events Sun Dec 12 22:09:02 2004
@@ -0,0 +1,14 @@
+#
+# VR5432 events
+#
+event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
+event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
+event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
+event:3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
+event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
+event:5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
+event:6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
+event:7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
+event:8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
+event:9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
+event:10 counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
diff -purN oprofile-0.8.1.orig/events/mips/vr5432/unit_masks oprofile-0.8.1/events/mips/vr5432/unit_masks
--- oprofile-0.8.1.orig/events/mips/vr5432/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/vr5432/unit_masks Sun Dec 12 22:16:51 2004
@@ -0,0 +1,5 @@
+#
+# MIPS VR5432 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/events/mips/vr5500/events oprofile-0.8.1/events/mips/vr5500/events
--- oprofile-0.8.1.orig/events/mips/vr5500/events Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/vr5500/events Sun Dec 12 22:10:11 2004
@@ -0,0 +1,16 @@
+#
+# VR5500, VR5532 and VR7701 events
+#
+# Very similar to what the VR5432 provides.
+#
+event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
+event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
+event:3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
+event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
+event:5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
+event:6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
+event:7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
+event:8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
+event:9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss
+event:10 counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss
diff -purN oprofile-0.8.1.orig/events/mips/vr5500/unit_masks oprofile-0.8.1/events/mips/vr5500/unit_masks
--- oprofile-0.8.1.orig/events/mips/vr5500/unit_masks Thu Jan 1 01:00:00 1970
+++ oprofile-0.8.1/events/mips/vr5500/unit_masks Sun Dec 12 22:16:57 2004
@@ -0,0 +1,5 @@
+#
+# MIPS VR5500 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff -purN oprofile-0.8.1.orig/libop/op_cpu_type.c oprofile-0.8.1/libop/op_cpu_type.c
--- oprofile-0.8.1.orig/libop/op_cpu_type.c Sat May 29 19:02:59 2004
+++ oprofile-0.8.1/libop/op_cpu_type.c Sun Dec 12 21:56:54 2004
@@ -43,6 +43,13 @@ static struct cpu_descr const cpu_descrs
{ "Pentium M (P6 core)", "i386/p6_mobile", CPU_P6_MOBILE, 2 },
{ "ARM/XScale PMU1", "arm/xscale1", CPU_ARM_XSCALE1, 3 },
{ "ARM/XScale PMU2", "arm/xscale2", CPU_ARM_XSCALE2, 5 },
+ { "MIPS R10000", "mips/r10000", CPU_MIPS_R10000, 2},
+ { "MIPS R12000", "mips/r12000", CPU_MIPS_R12000, 4},
+ { "QED RM7000", "mips/rm7000", CPU_MIPS_RM7000, 1},
+ { "PMC-Sierra RM9000", "mips/rm9000", CPU_MIPS_RM9000, 2},
+ { "Sibyte SB1", "mips/sb1", CPU_MIPS_SB1, 4},
+ { "NEC VR5432", "mips/vr5432", CPU_MIPS_VR5432, 2},
+ { "NEC VR5500", "mips/vr5500", CPU_MIPS_VR5500, 2},
};
static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
diff -purN oprofile-0.8.1.orig/libop/op_cpu_type.h oprofile-0.8.1/libop/op_cpu_type.h
--- oprofile-0.8.1.orig/libop/op_cpu_type.h Sat May 29 19:02:59 2004
+++ oprofile-0.8.1/libop/op_cpu_type.h Sun Dec 12 21:41:21 2004
@@ -39,6 +39,13 @@ typedef enum {
CPU_P6_MOBILE, /**< Pentium M series */
CPU_ARM_XSCALE1, /**< ARM XScale 1 */
CPU_ARM_XSCALE2, /**< ARM XScale 2 */
+ CPU_MIPS_R10000, /**< MIPS R10000 */
+ CPU_MIPS_R12000, /**< MIPS R12000 */
+ CPU_MIPS_RM7000, /**< QED RM7000 */
+ CPU_MIPS_RM9000, /**< PMC-Sierra RM9000 */
+ CPU_MIPS_SB1, /**< Broadcom SB1 */
+ CPU_MIPS_VR5432, /**< NEC VR5432 */
+ CPU_MIPS_VR5500, /**< MIPS VR5500, VR5532 and VR7701 */
MAX_CPU_TYPE
} op_cpu;
diff -purN oprofile-0.8.1.orig/libop/op_events.c oprofile-0.8.1/libop/op_events.c
--- oprofile-0.8.1.orig/libop/op_events.c Sat May 29 19:02:59 2004
+++ oprofile-0.8.1/libop/op_events.c Sun Dec 12 22:10:30 2004
@@ -651,6 +651,25 @@ void op_default_event(op_cpu cpu_type, s
descr->name = "CPU_CYCLES";
break;
+ case CPU_MIPS_R10000:
+ case CPU_MIPS_R12000:
+ descr->name = "INSTRUCTIONS_GRADUATED";
+ break;
+
+ case CPU_MIPS_RM7000:
+ case CPU_MIPS_RM9000:
+ descr->name = "INSTRUCTIONS_ISSUED";
+ break;
+
+ case CPU_MIPS_SB1:
+ descr->name = "INSN_SURVIVED_STAGE7";
+ break;
+
+ case CPU_MIPS_VR5432:
+ case CPU_MIPS_VR5500:
+ descr->name = "INSTRUCTIONS_EXECUTED";
+ break;
+
// don't use default, if someone add a cpu he wants a compiler
// warning if he forgets to handle it here.
case CPU_TIMER_INT:
|