>> - is it possible to configure the FPGA in the chain?
> Now i CAN configure the prom, and then the prom configures fine the
> FPGA, but i couldnt configure the FPGA bypassing the PROM.
Just to understand this properly: configuration of the PROM works fine
when the FPGA is bypassed (i.e. both are part of the scan chain)? Or
does this only work when the FPGA is removed from the chain?
> There is no error message, it send the bits but nothing is
> programmed. The fpga "done" signal dosnt shine :(
> [...] jtag> svf /home/jpablo/comp/jpablo/ejemplotestfpga.svf
Is this the same file you use when configuring the FPGA standalone
> Warning svf: checking of TDO not supported for SIR. This message is
> only displayed once.
That's all a bit strange. I expected some errors but there aren't any.
The SVFs for my Spartan IIe perform only a few checks on TDO, but at
least the IDCODE is verified. The fact that you encounter no errors at
all tells us that the basic communication works, I guess. I.e. the PROM
seems to be bypassed properly.
The xc18v01 uses one of the serial or parallel modes to configure the
FPGA. Do you use a slave variant? At least for the slave modes, the PROM
needs to drive PROGRAM# at the FPGA. This could influence configuration
via JTAG. What happens when the FPGA is set to boundary-scan mode via M2-M0?
Quote from the data sheet:
Configuration through the boundary-scan port is always available,
independent of the mode selection. Selecting the boundary-scan mode
simply turns off the other modes.
> I can work now, programming the prom its ok for me, but it would be
> nice to have it working like it should :)